1 /*************************************************************************** 2 * Copyright (c) 1999-2009, Broadcom Corporation. 3 * 4 * Name: bcm_70012_regs.h 5 * 6 * Description: BCM70012 registers 7 * 8 ******************************************************************** 9 * This header is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU Lesser General Public License as published 11 * by the Free Software Foundation, either version 2.1 of the License. 12 * 13 * This header is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU Lesser General Public License for more details. 17 * You should have received a copy of the GNU Lesser General Public License 18 * along with this header. If not, see <http://www.gnu.org/licenses/>. 19 ***************************************************************************/ 20 21 #ifndef MACFILE_H__ 22 #define MACFILE_H__ 23 24 /** 25 * m = memory, c = core, r = register, f = field, d = data. 26 */ 27 #if !defined(GET_FIELD) && !defined(SET_FIELD) 28 #define BRCM_ALIGN(c, r, f) c##_##r##_##f##_ALIGN 29 #define BRCM_BITS(c, r, f) c##_##r##_##f##_BITS 30 #define BRCM_MASK(c, r, f) c##_##r##_##f##_MASK 31 #define BRCM_SHIFT(c, r, f) c##_##r##_##f##_SHIFT 32 33 #define GET_FIELD(m, c, r, f) \ 34 ((((m) & BRCM_MASK(c, r, f)) >> BRCM_SHIFT(c, r, f)) << BRCM_ALIGN(c, r, f)) 35 36 #define SET_FIELD(m, c, r, f, d) \ 37 ((m) = (((m) & ~BRCM_MASK(c, r, f)) | ((((d) >> BRCM_ALIGN(c, r, f)) << \ 38 BRCM_SHIFT(c, r, f)) & BRCM_MASK(c, r, f))) \ 39 ) 40 41 #define SET_TYPE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##d) 42 #define SET_NAME_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##r##_##f##_##d) 43 #define SET_VALUE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, d) 44 45 #endif /* GET & SET */ 46 47 /**************************************************************************** 48 * Core Enums. 49 ***************************************************************************/ 50 /**************************************************************************** 51 * Enums: AES_RGR_BRIDGE_RESET_CTRL 52 ***************************************************************************/ 53 #define AES_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 54 #define AES_RGR_BRIDGE_RESET_CTRL_ASSERT 1 55 56 /**************************************************************************** 57 * Enums: CCE_RGR_BRIDGE_RESET_CTRL 58 ***************************************************************************/ 59 #define CCE_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 60 #define CCE_RGR_BRIDGE_RESET_CTRL_ASSERT 1 61 62 /**************************************************************************** 63 * Enums: DBU_RGR_BRIDGE_RESET_CTRL 64 ***************************************************************************/ 65 #define DBU_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 66 #define DBU_RGR_BRIDGE_RESET_CTRL_ASSERT 1 67 68 /**************************************************************************** 69 * Enums: DCI_RGR_BRIDGE_RESET_CTRL 70 ***************************************************************************/ 71 #define DCI_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 72 #define DCI_RGR_BRIDGE_RESET_CTRL_ASSERT 1 73 74 /**************************************************************************** 75 * Enums: GISB_ARBITER_DEASSERT_ASSERT 76 ***************************************************************************/ 77 #define GISB_ARBITER_DEASSERT_ASSERT_DEASSERT 0 78 #define GISB_ARBITER_DEASSERT_ASSERT_ASSERT 1 79 80 /**************************************************************************** 81 * Enums: GISB_ARBITER_UNMASK_MASK 82 ***************************************************************************/ 83 #define GISB_ARBITER_UNMASK_MASK_UNMASK 0 84 #define GISB_ARBITER_UNMASK_MASK_MASK 1 85 86 /**************************************************************************** 87 * Enums: GISB_ARBITER_DISABLE_ENABLE 88 ***************************************************************************/ 89 #define GISB_ARBITER_DISABLE_ENABLE_DISABLE 0 90 #define GISB_ARBITER_DISABLE_ENABLE_ENABLE 1 91 92 /**************************************************************************** 93 * Enums: I2C_GR_BRIDGE_RESET_CTRL 94 ***************************************************************************/ 95 #define I2C_GR_BRIDGE_RESET_CTRL_DEASSERT 0 96 #define I2C_GR_BRIDGE_RESET_CTRL_ASSERT 1 97 98 /**************************************************************************** 99 * Enums: MISC_GR_BRIDGE_RESET_CTRL 100 ***************************************************************************/ 101 #define MISC_GR_BRIDGE_RESET_CTRL_DEASSERT 0 102 #define MISC_GR_BRIDGE_RESET_CTRL_ASSERT 1 103 104 /**************************************************************************** 105 * Enums: OTP_GR_BRIDGE_RESET_CTRL 106 ***************************************************************************/ 107 #define OTP_GR_BRIDGE_RESET_CTRL_DEASSERT 0 108 #define OTP_GR_BRIDGE_RESET_CTRL_ASSERT 1 109 110 /**************************************************************************** 111 * BCM70012_TGT_TOP_PCIE_CFG 112 ***************************************************************************/ 113 #define PCIE_CFG_DEVICE_VENDOR_ID 0x00000000 /* DEVICE_VENDOR_ID Register */ 114 #define PCIE_CFG_STATUS_COMMAND 0x00000004 /* STATUS_COMMAND Register */ 115 #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID 0x00000008 /* PCI_CLASSCODE_AND_REVISION_ID Register */ 116 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE 0x0000000c /* BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE Register */ 117 #define PCIE_CFG_BASE_ADDRESS_1 0x00000010 /* BASE_ADDRESS_1 Register */ 118 #define PCIE_CFG_BASE_ADDRESS_2 0x00000014 /* BASE_ADDRESS_2 Register */ 119 #define PCIE_CFG_BASE_ADDRESS_3 0x00000018 /* BASE_ADDRESS_3 Register */ 120 #define PCIE_CFG_BASE_ADDRESS_4 0x0000001c /* BASE_ADDRESS_4 Register */ 121 #define PCIE_CFG_CARDBUS_CIS_POINTER 0x00000028 /* CARDBUS_CIS_POINTER Register */ 122 #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID 0x0000002c /* SUBSYSTEM_DEVICE_VENDOR_ID Register */ 123 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS 0x00000030 /* EXPANSION_ROM_BASE_ADDRESS Register */ 124 #define PCIE_CFG_CAPABILITIES_POINTER 0x00000034 /* CAPABILITIES_POINTER Register */ 125 #define PCIE_CFG_INTERRUPT 0x0000003c /* INTERRUPT Register */ 126 #define PCIE_CFG_VPD_CAPABILITIES 0x00000040 /* VPD_CAPABILITIES Register */ 127 #define PCIE_CFG_VPD_DATA 0x00000044 /* VPD_DATA Register */ 128 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY 0x00000048 /* POWER_MANAGEMENT_CAPABILITY Register */ 129 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS 0x0000004c /* POWER_MANAGEMENT_CONTROL_STATUS Register */ 130 #define PCIE_CFG_MSI_CAPABILITY_HEADER 0x00000050 /* MSI_CAPABILITY_HEADER Register */ 131 #define PCIE_CFG_MSI_LOWER_ADDRESS 0x00000054 /* MSI_LOWER_ADDRESS Register */ 132 #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER 0x00000058 /* MSI_UPPER_ADDRESS_REGISTER Register */ 133 #define PCIE_CFG_MSI_DATA 0x0000005c /* MSI_DATA Register */ 134 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER 0x00000060 /* BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER Register */ 135 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES 0x00000064 /* RESET_COUNTERS_INITIAL_VALUES Register */ 136 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL 0x00000068 /* MISCELLANEOUS_HOST_CONTROL Register */ 137 #define PCIE_CFG_SPARE 0x0000006c /* SPARE Register */ 138 #define PCIE_CFG_PCI_STATE 0x00000070 /* PCI_STATE Register */ 139 #define PCIE_CFG_CLOCK_CONTROL 0x00000074 /* CLOCK_CONTROL Register */ 140 #define PCIE_CFG_REGISTER_BASE 0x00000078 /* REGISTER_BASE Register */ 141 #define PCIE_CFG_MEMORY_BASE 0x0000007c /* MEMORY_BASE Register */ 142 #define PCIE_CFG_REGISTER_DATA 0x00000080 /* REGISTER_DATA Register */ 143 #define PCIE_CFG_MEMORY_DATA 0x00000084 /* MEMORY_DATA Register */ 144 #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE 0x00000088 /* EXPANSION_ROM_BAR_SIZE Register */ 145 #define PCIE_CFG_EXPANSION_ROM_ADDRESS 0x0000008c /* EXPANSION_ROM_ADDRESS Register */ 146 #define PCIE_CFG_EXPANSION_ROM_DATA 0x00000090 /* EXPANSION_ROM_DATA Register */ 147 #define PCIE_CFG_VPD_INTERFACE 0x00000094 /* VPD_INTERFACE Register */ 148 #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER 0x00000098 /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER Register */ 149 #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER 0x0000009c /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER Register */ 150 #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER 0x000000a0 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER Register */ 151 #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER 0x000000a4 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER Register */ 152 #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER 0x000000a8 /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER Register */ 153 #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER 0x000000ac /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER Register */ 154 #define PCIE_CFG_INT_MAILBOX_UPPER 0x000000b0 /* INT_MAILBOX_UPPER Register */ 155 #define PCIE_CFG_INT_MAILBOX_LOWER 0x000000b4 /* INT_MAILBOX_LOWER Register */ 156 #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION 0x000000bc /* PRODUCT_ID_AND_ASIC_REVISION Register */ 157 #define PCIE_CFG_FUNCTION_EVENT 0x000000c0 /* FUNCTION_EVENT Register */ 158 #define PCIE_CFG_FUNCTION_EVENT_MASK 0x000000c4 /* FUNCTION_EVENT_MASK Register */ 159 #define PCIE_CFG_FUNCTION_PRESENT 0x000000c8 /* FUNCTION_PRESENT Register */ 160 #define PCIE_CFG_PCIE_CAPABILITIES 0x000000cc /* PCIE_CAPABILITIES Register */ 161 #define PCIE_CFG_DEVICE_CAPABILITIES 0x000000d0 /* DEVICE_CAPABILITIES Register */ 162 #define PCIE_CFG_DEVICE_STATUS_CONTROL 0x000000d4 /* DEVICE_STATUS_CONTROL Register */ 163 #define PCIE_CFG_LINK_CAPABILITY 0x000000d8 /* LINK_CAPABILITY Register */ 164 #define PCIE_CFG_LINK_STATUS_CONTROL 0x000000dc /* LINK_STATUS_CONTROL Register */ 165 #define PCIE_CFG_DEVICE_CAPABILITIES_2 0x000000f0 /* DEVICE_CAPABILITIES_2 Register */ 166 #define PCIE_CFG_DEVICE_STATUS_CONTROL_2 0x000000f4 /* DEVICE_STATUS_CONTROL_2 Register */ 167 #define PCIE_CFG_LINK_CAPABILITIES_2 0x000000f8 /* LINK_CAPABILITIES_2 Register */ 168 #define PCIE_CFG_LINK_STATUS_CONTROL_2 0x000000fc /* LINK_STATUS_CONTROL_2 Register */ 169 #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER 0x00000100 /* ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER Register */ 170 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS 0x00000104 /* UNCORRECTABLE_ERROR_STATUS Register */ 171 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK 0x00000108 /* UNCORRECTABLE_ERROR_MASK Register */ 172 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY 0x0000010c /* UNCORRECTABLE_ERROR_SEVERITY Register */ 173 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS 0x00000110 /* CORRECTABLE_ERROR_STATUS Register */ 174 #define PCIE_CFG_CORRECTABLE_ERROR_MASK 0x00000114 /* CORRECTABLE_ERROR_MASK Register */ 175 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL 0x00000118 /* ADVANCED_ERROR_CAPABILITIES_AND_CONTROL Register */ 176 #define PCIE_CFG_HEADER_LOG_1 0x0000011c /* HEADER_LOG_1 Register */ 177 #define PCIE_CFG_HEADER_LOG_2 0x00000120 /* HEADER_LOG_2 Register */ 178 #define PCIE_CFG_HEADER_LOG_3 0x00000124 /* HEADER_LOG_3 Register */ 179 #define PCIE_CFG_HEADER_LOG_4 0x00000128 /* HEADER_LOG_4 Register */ 180 #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER 0x0000013c /* VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER Register */ 181 #define PCIE_CFG_PORT_VC_CAPABILITY 0x00000140 /* PORT_VC_CAPABILITY Register */ 182 #define PCIE_CFG_PORT_VC_CAPABILITY_2 0x00000144 /* PORT_VC_CAPABILITY_2 Register */ 183 #define PCIE_CFG_PORT_VC_STATUS_CONTROL 0x00000148 /* PORT_VC_STATUS_CONTROL Register */ 184 #define PCIE_CFG_VC_RESOURCE_CAPABILITY 0x0000014c /* VC_RESOURCE_CAPABILITY Register */ 185 #define PCIE_CFG_VC_RESOURCE_CONTROL 0x00000150 /* VC_RESOURCE_CONTROL Register */ 186 #define PCIE_CFG_VC_RESOURCE_STATUS 0x00000154 /* VC_RESOURCE_STATUS Register */ 187 #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER 0x00000160 /* DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER Register */ 188 #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW 0x00000164 /* DEVICE_SERIAL_NO_LOWER_DW Register */ 189 #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW 0x00000168 /* DEVICE_SERIAL_NO_UPPER_DW Register */ 190 #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER 0x0000016c /* POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER Register */ 191 #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT 0x00000170 /* POWER_BUDGETING_DATA_SELECT Register */ 192 #define PCIE_CFG_POWER_BUDGETING_DATA 0x00000174 /* POWER_BUDGETING_DATA Register */ 193 #define PCIE_CFG_POWER_BUDGETING_CAPABILITY 0x00000178 /* POWER_BUDGETING_CAPABILITY Register */ 194 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1 0x0000017c /* FIRMWARE_POWER_BUDGETING_2_1 Register */ 195 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3 0x00000180 /* FIRMWARE_POWER_BUDGETING_4_3 Register */ 196 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5 0x00000184 /* FIRMWARE_POWER_BUDGETING_6_5 Register */ 197 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7 0x00000188 /* FIRMWARE_POWER_BUDGETING_8_7 Register */ 198 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING 0x0000018c /* PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING Register */ 199 200 201 /**************************************************************************** 202 * BCM70012_TGT_TOP_PCIE_TL 203 ***************************************************************************/ 204 #define PCIE_TL_TL_CONTROL 0x00000400 /* TL_CONTROL Register */ 205 #define PCIE_TL_TRANSACTION_CONFIGURATION 0x00000404 /* TRANSACTION_CONFIGURATION Register */ 206 207 208 /**************************************************************************** 209 * BCM70012_TGT_TOP_PCIE_DLL 210 ***************************************************************************/ 211 #define PCIE_DLL_DATA_LINK_CONTROL 0x00000500 /* DATA_LINK_CONTROL Register */ 212 #define PCIE_DLL_DATA_LINK_STATUS 0x00000504 /* DATA_LINK_STATUS Register */ 213 214 215 /**************************************************************************** 216 * BCM70012_TGT_TOP_INTR 217 ***************************************************************************/ 218 #define INTR_INTR_STATUS 0x00000700 /* Interrupt Status Register */ 219 #define INTR_INTR_SET 0x00000704 /* Interrupt Set Register */ 220 #define INTR_INTR_CLR_REG 0x00000708 /* Interrupt Clear Register */ 221 #define INTR_INTR_MSK_STS_REG 0x0000070c /* Interrupt Mask Status Register */ 222 #define INTR_INTR_MSK_SET_REG 0x00000710 /* Interrupt Mask Set Register */ 223 #define INTR_INTR_MSK_CLR_REG 0x00000714 /* Interrupt Mask Clear Register */ 224 #define INTR_EOI_CTRL 0x00000720 /* End of interrupt control register */ 225 226 227 /**************************************************************************** 228 * BCM70012_MISC_TOP_MISC1 229 ***************************************************************************/ 230 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0 0x00000c00 /* Tx DMA Descriptor List0 First Descriptor lower Address */ 231 #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0 0x00000c04 /* Tx DMA Descriptor List0 First Descriptor Upper Address */ 232 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1 0x00000c08 /* Tx DMA Descriptor List1 First Descriptor Lower Address */ 233 #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1 0x00000c0c /* Tx DMA Descriptor List1 First Descriptor Upper Address */ 234 #define MISC1_TX_SW_DESC_LIST_CTRL_STS 0x00000c10 /* Tx DMA Software Descriptor List Control and Status */ 235 #define MISC1_TX_DMA_ERROR_STATUS 0x00000c18 /* Tx DMA Engine Error Status */ 236 #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR 0x00000c1c /* Tx DMA List0 Current Descriptor Lower Address */ 237 #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR 0x00000c20 /* Tx DMA List0 Current Descriptor Upper Address */ 238 #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM 0x00000c24 /* Tx DMA List0 Current Descriptor Upper Address */ 239 #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR 0x00000c28 /* Tx DMA List1 Current Descriptor Lower Address */ 240 #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR 0x00000c2c /* Tx DMA List1 Current Descriptor Upper Address */ 241 #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM 0x00000c30 /* Tx DMA List1 Current Descriptor Upper Address */ 242 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0 0x00000c34 /* Y Rx Descriptor List0 First Descriptor Lower Address */ 243 #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0 0x00000c38 /* Y Rx Descriptor List0 First Descriptor Upper Address */ 244 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1 0x00000c3c /* Y Rx Descriptor List1 First Descriptor Lower Address */ 245 #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1 0x00000c40 /* Y Rx Descriptor List1 First Descriptor Upper Address */ 246 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS 0x00000c44 /* Y Rx Software Descriptor List Control and Status */ 247 #define MISC1_Y_RX_ERROR_STATUS 0x00000c4c /* Y Rx Engine Error Status */ 248 #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR 0x00000c50 /* Y Rx List0 Current Descriptor Lower Address */ 249 #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR 0x00000c54 /* Y Rx List0 Current Descriptor Upper Address */ 250 #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT 0x00000c58 /* Y Rx List0 Current Descriptor Byte Count */ 251 #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR 0x00000c5c /* Y Rx List1 Current Descriptor Lower address */ 252 #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR 0x00000c60 /* Y Rx List1 Current Descriptor Upper address */ 253 #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT 0x00000c64 /* Y Rx List1 Current Descriptor Byte Count */ 254 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0 0x00000c68 /* UV Rx Descriptor List0 First Descriptor lower Address */ 255 #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0 0x00000c6c /* UV Rx Descriptor List0 First Descriptor Upper Address */ 256 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1 0x00000c70 /* UV Rx Descriptor List1 First Descriptor Lower Address */ 257 #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1 0x00000c74 /* UV Rx Descriptor List1 First Descriptor Upper Address */ 258 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS 0x00000c78 /* UV Rx Software Descriptor List Control and Status */ 259 #define MISC1_UV_RX_ERROR_STATUS 0x00000c7c /* UV Rx Engine Error Status */ 260 #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR 0x00000c80 /* UV Rx List0 Current Descriptor Lower Address */ 261 #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR 0x00000c84 /* UV Rx List0 Current Descriptor Upper Address */ 262 #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT 0x00000c88 /* UV Rx List0 Current Descriptor Byte Count */ 263 #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR 0x00000c8c /* UV Rx List1 Current Descriptor Lower Address */ 264 #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR 0x00000c90 /* UV Rx List1 Current Descriptor Upper Address */ 265 #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT 0x00000c94 /* UV Rx List1 Current Descriptor Byte Count */ 266 #define MISC1_DMA_DEBUG_OPTIONS_REG 0x00000c98 /* DMA Debug Options Register */ 267 #define MISC1_READ_CHANNEL_ERROR_STATUS 0x00000c9c /* Read Channel Error Status */ 268 #define MISC1_PCIE_DMA_CTRL 0x00000ca0 /* PCIE DMA Control Register */ 269 270 271 /**************************************************************************** 272 * BCM70012_MISC_TOP_MISC2 273 ***************************************************************************/ 274 #define MISC2_GLOBAL_CTRL 0x00000d00 /* Global Control Register */ 275 #define MISC2_INTERNAL_STATUS 0x00000d04 /* Internal Status Register */ 276 #define MISC2_INTERNAL_STATUS_MUX_CTRL 0x00000d08 /* Internal Debug Mux Control */ 277 #define MISC2_DEBUG_FIFO_LENGTH 0x00000d0c /* Debug FIFO Length */ 278 279 280 /**************************************************************************** 281 * BCM70012_MISC_TOP_MISC3 282 ***************************************************************************/ 283 #define MISC3_RESET_CTRL 0x00000e00 /* Reset Control Register */ 284 #define MISC3_BIST_CTRL 0x00000e04 /* BIST Control Register */ 285 #define MISC3_BIST_STATUS 0x00000e08 /* BIST Status Register */ 286 #define MISC3_RX_CHECKSUM 0x00000e0c /* Receive Checksum */ 287 #define MISC3_TX_CHECKSUM 0x00000e10 /* Transmit Checksum */ 288 #define MISC3_ECO_CTRL_CORE 0x00000e14 /* ECO Core Reset Control Register */ 289 #define MISC3_CSI_TEST_CTRL 0x00000e18 /* CSI Test Control Register */ 290 #define MISC3_HD_DVI_TEST_CTRL 0x00000e1c /* HD DVI Test Control Register */ 291 292 293 /**************************************************************************** 294 * BCM70012_MISC_TOP_MISC_PERST 295 ***************************************************************************/ 296 #define MISC_PERST_ECO_CTRL_PERST 0x00000e80 /* ECO PCIE Reset Control Register */ 297 #define MISC_PERST_DECODER_CTRL 0x00000e84 /* Decoder Control Register */ 298 #define MISC_PERST_CCE_STATUS 0x00000e88 /* Config Copy Engine Status */ 299 #define MISC_PERST_PCIE_DEBUG 0x00000e8c /* PCIE Debug Control Register */ 300 #define MISC_PERST_PCIE_DEBUG_STATUS 0x00000e90 /* PCIE Debug Status Register */ 301 #define MISC_PERST_VREG_CTRL 0x00000e94 /* Voltage Regulator Control Register */ 302 #define MISC_PERST_MEM_CTRL 0x00000e98 /* Memory Control Register */ 303 #define MISC_PERST_CLOCK_CTRL 0x00000e9c /* Clock Control Register */ 304 305 306 /**************************************************************************** 307 * BCM70012_MISC_TOP_GISB_ARBITER 308 ***************************************************************************/ 309 #define GISB_ARBITER_REVISION 0x00000f00 /* GISB ARBITER REVISION */ 310 #define GISB_ARBITER_SCRATCH 0x00000f04 /* GISB ARBITER Scratch Register */ 311 #define GISB_ARBITER_REQ_MASK 0x00000f08 /* GISB ARBITER Master Request Mask Register */ 312 #define GISB_ARBITER_TIMER 0x00000f0c /* GISB ARBITER Timer Value Register */ 313 314 315 /**************************************************************************** 316 * BCM70012_OTP_TOP_OTP 317 ***************************************************************************/ 318 #define OTP_CONFIG_INFO 0x00001400 /* OTP Configuration Register */ 319 #define OTP_CMD 0x00001404 /* OTP Command Register */ 320 #define OTP_STATUS 0x00001408 /* OTP Status Register */ 321 #define OTP_CONTENT_MISC 0x0000140c /* Content : Miscellaneous Register */ 322 #define OTP_CONTENT_AES_0 0x00001410 /* Content : AES Key 0 Register */ 323 #define OTP_CONTENT_AES_1 0x00001414 /* Content : AES Key 1 Register */ 324 #define OTP_CONTENT_AES_2 0x00001418 /* Content : AES Key 2 Register */ 325 #define OTP_CONTENT_AES_3 0x0000141c /* Content : AES Key 3 Register */ 326 #define OTP_CONTENT_SHA_0 0x00001420 /* Content : SHA Key 0 Register */ 327 #define OTP_CONTENT_SHA_1 0x00001424 /* Content : SHA Key 1 Register */ 328 #define OTP_CONTENT_SHA_2 0x00001428 /* Content : SHA Key 2 Register */ 329 #define OTP_CONTENT_SHA_3 0x0000142c /* Content : SHA Key 3 Register */ 330 #define OTP_CONTENT_SHA_4 0x00001430 /* Content : SHA Key 4 Register */ 331 #define OTP_CONTENT_SHA_5 0x00001434 /* Content : SHA Key 5 Register */ 332 #define OTP_CONTENT_SHA_6 0x00001438 /* Content : SHA Key 6 Register */ 333 #define OTP_CONTENT_SHA_7 0x0000143c /* Content : SHA Key 7 Register */ 334 #define OTP_CONTENT_CHECKSUM 0x00001440 /* Content : Checksum Register */ 335 #define OTP_PROG_CTRL 0x00001444 /* Programming Control Register */ 336 #define OTP_PROG_STATUS 0x00001448 /* Programming Status Register */ 337 #define OTP_PROG_PULSE 0x0000144c /* Program Pulse Width Register */ 338 #define OTP_VERIFY_PULSE 0x00001450 /* Verify Pulse Width Register */ 339 #define OTP_PROG_MASK 0x00001454 /* Program Mask Register */ 340 #define OTP_DATA_INPUT 0x00001458 /* Data Input Register */ 341 #define OTP_DATA_OUTPUT 0x0000145c /* Data Output Register */ 342 343 344 /**************************************************************************** 345 * BCM70012_AES_TOP_AES 346 ***************************************************************************/ 347 #define AES_CONFIG_INFO 0x00001800 /* AES Configuration Information Register */ 348 #define AES_CMD 0x00001804 /* AES Command Register */ 349 #define AES_STATUS 0x00001808 /* AES Status Register */ 350 #define AES_EEPROM_CONFIG 0x0000180c /* AES EEPROM Configuration Register */ 351 #define AES_EEPROM_DATA_0 0x00001810 /* AES EEPROM Data Register 0 */ 352 #define AES_EEPROM_DATA_1 0x00001814 /* AES EEPROM Data Register 1 */ 353 #define AES_EEPROM_DATA_2 0x00001818 /* AES EEPROM Data Register 2 */ 354 #define AES_EEPROM_DATA_3 0x0000181c /* AES EEPROM Data Register 3 */ 355 356 357 /**************************************************************************** 358 * BCM70012_DCI_TOP_DCI 359 ***************************************************************************/ 360 #define DCI_CMD 0x00001c00 /* DCI Command Register */ 361 #define DCI_STATUS 0x00001c04 /* DCI Status Register */ 362 #define DCI_DRAM_BASE_ADDR 0x00001c08 /* DRAM Base Address Register */ 363 #define DCI_FIRMWARE_ADDR 0x00001c0c /* Firmware Address Register */ 364 #define DCI_FIRMWARE_DATA 0x00001c10 /* Firmware Data Register */ 365 #define DCI_SIGNATURE_DATA_0 0x00001c14 /* Signature Data Register 0 */ 366 #define DCI_SIGNATURE_DATA_1 0x00001c18 /* Signature Data Register 1 */ 367 #define DCI_SIGNATURE_DATA_2 0x00001c1c /* Signature Data Register 2 */ 368 #define DCI_SIGNATURE_DATA_3 0x00001c20 /* Signature Data Register 3 */ 369 #define DCI_SIGNATURE_DATA_4 0x00001c24 /* Signature Data Register 4 */ 370 #define DCI_SIGNATURE_DATA_5 0x00001c28 /* Signature Data Register 5 */ 371 #define DCI_SIGNATURE_DATA_6 0x00001c2c /* Signature Data Register 6 */ 372 #define DCI_SIGNATURE_DATA_7 0x00001c30 /* Signature Data Register 7 */ 373 374 375 /**************************************************************************** 376 * BCM70012_TGT_TOP_INTR 377 ***************************************************************************/ 378 /**************************************************************************** 379 * INTR :: INTR_STATUS 380 ***************************************************************************/ 381 /* INTR :: INTR_STATUS :: reserved0 [31:26] */ 382 #define INTR_INTR_STATUS_reserved0_MASK 0xfc000000 383 #define INTR_INTR_STATUS_reserved0_ALIGN 0 384 #define INTR_INTR_STATUS_reserved0_BITS 6 385 #define INTR_INTR_STATUS_reserved0_SHIFT 26 386 387 /* INTR :: INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ 388 #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 389 #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_ALIGN 0 390 #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_BITS 1 391 #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 392 393 /* INTR :: INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ 394 #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 395 #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_ALIGN 0 396 #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_BITS 1 397 #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 398 399 /* INTR :: INTR_STATUS :: reserved1 [23:14] */ 400 #define INTR_INTR_STATUS_reserved1_MASK 0x00ffc000 401 #define INTR_INTR_STATUS_reserved1_ALIGN 0 402 #define INTR_INTR_STATUS_reserved1_BITS 10 403 #define INTR_INTR_STATUS_reserved1_SHIFT 14 404 405 /* INTR :: INTR_STATUS :: L1_UV_RX_DMA_ERR_INTR [13:13] */ 406 #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK 0x00002000 407 #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_ALIGN 0 408 #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_BITS 1 409 #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_SHIFT 13 410 411 /* INTR :: INTR_STATUS :: L1_UV_RX_DMA_DONE_INTR [12:12] */ 412 #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK 0x00001000 413 #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_ALIGN 0 414 #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_BITS 1 415 #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_SHIFT 12 416 417 /* INTR :: INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ 418 #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 419 #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_ALIGN 0 420 #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_BITS 1 421 #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 422 423 /* INTR :: INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ 424 #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 425 #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_ALIGN 0 426 #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_BITS 1 427 #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 428 429 /* INTR :: INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ 430 #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 431 #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_ALIGN 0 432 #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_BITS 1 433 #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 434 435 /* INTR :: INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ 436 #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 437 #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_ALIGN 0 438 #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_BITS 1 439 #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 440 441 /* INTR :: INTR_STATUS :: reserved2 [07:06] */ 442 #define INTR_INTR_STATUS_reserved2_MASK 0x000000c0 443 #define INTR_INTR_STATUS_reserved2_ALIGN 0 444 #define INTR_INTR_STATUS_reserved2_BITS 2 445 #define INTR_INTR_STATUS_reserved2_SHIFT 6 446 447 /* INTR :: INTR_STATUS :: L0_UV_RX_DMA_ERR_INTR [05:05] */ 448 #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK 0x00000020 449 #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_ALIGN 0 450 #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_BITS 1 451 #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_SHIFT 5 452 453 /* INTR :: INTR_STATUS :: L0_UV_RX_DMA_DONE_INTR [04:04] */ 454 #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK 0x00000010 455 #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_ALIGN 0 456 #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_BITS 1 457 #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_SHIFT 4 458 459 /* INTR :: INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ 460 #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 461 #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_ALIGN 0 462 #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_BITS 1 463 #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 464 465 /* INTR :: INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ 466 #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 467 #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_ALIGN 0 468 #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_BITS 1 469 #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 470 471 /* INTR :: INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ 472 #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 473 #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_ALIGN 0 474 #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_BITS 1 475 #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 476 477 /* INTR :: INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ 478 #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 479 #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_ALIGN 0 480 #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_BITS 1 481 #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 482 483 484 /**************************************************************************** 485 * MISC1 :: TX_SW_DESC_LIST_CTRL_STS 486 ***************************************************************************/ 487 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ 488 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 489 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 490 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 491 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 492 493 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ 494 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 495 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 496 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 497 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 498 499 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ 500 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 501 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 502 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 503 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 504 505 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_HALT_ON_ERROR [01:01] */ 506 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK 0x00000002 507 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_ALIGN 0 508 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_BITS 1 509 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT 1 510 511 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ 512 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 513 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_ALIGN 0 514 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_BITS 1 515 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0 516 517 518 /**************************************************************************** 519 * MISC1 :: TX_DMA_ERROR_STATUS 520 ***************************************************************************/ 521 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved0 [31:10] */ 522 #define MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK 0xfffffc00 523 #define MISC1_TX_DMA_ERROR_STATUS_reserved0_ALIGN 0 524 #define MISC1_TX_DMA_ERROR_STATUS_reserved0_BITS 22 525 #define MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT 10 526 527 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */ 528 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 529 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 530 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_BITS 1 531 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 532 533 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved1 [08:08] */ 534 #define MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK 0x00000100 535 #define MISC1_TX_DMA_ERROR_STATUS_reserved1_ALIGN 0 536 #define MISC1_TX_DMA_ERROR_STATUS_reserved1_BITS 1 537 #define MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT 8 538 539 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */ 540 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 541 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 542 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_BITS 1 543 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 544 545 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved2 [06:06] */ 546 #define MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK 0x00000040 547 #define MISC1_TX_DMA_ERROR_STATUS_reserved2_ALIGN 0 548 #define MISC1_TX_DMA_ERROR_STATUS_reserved2_BITS 1 549 #define MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT 6 550 551 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DMA_DATA_TX_ABORT_ERRORS [05:05] */ 552 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000020 553 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 554 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_BITS 1 555 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT 5 556 557 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_FIFO_FULL_ERRORS [04:04] */ 558 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 559 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_ALIGN 0 560 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_BITS 1 561 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT 4 562 563 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved3 [03:03] */ 564 #define MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK 0x00000008 565 #define MISC1_TX_DMA_ERROR_STATUS_reserved3_ALIGN 0 566 #define MISC1_TX_DMA_ERROR_STATUS_reserved3_BITS 1 567 #define MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT 3 568 569 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DMA_DATA_TX_ABORT_ERRORS [02:02] */ 570 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000004 571 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 572 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_BITS 1 573 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT 2 574 575 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_FIFO_FULL_ERRORS [01:01] */ 576 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 577 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_ALIGN 0 578 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_BITS 1 579 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT 1 580 581 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved4 [00:00] */ 582 #define MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK 0x00000001 583 #define MISC1_TX_DMA_ERROR_STATUS_reserved4_ALIGN 0 584 #define MISC1_TX_DMA_ERROR_STATUS_reserved4_BITS 1 585 #define MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT 0 586 587 588 /**************************************************************************** 589 * MISC1 :: Y_RX_ERROR_STATUS 590 ***************************************************************************/ 591 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved0 [31:14] */ 592 #define MISC1_Y_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 593 #define MISC1_Y_RX_ERROR_STATUS_reserved0_ALIGN 0 594 #define MISC1_Y_RX_ERROR_STATUS_reserved0_BITS 18 595 #define MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT 14 596 597 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ 598 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 599 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 600 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 601 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 602 603 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ 604 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 605 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 606 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 607 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 608 609 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ 610 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 611 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 612 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 613 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 614 615 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ 616 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 617 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 618 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 619 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 620 621 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ 622 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 623 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 624 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 625 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 626 627 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved1 [08:08] */ 628 #define MISC1_Y_RX_ERROR_STATUS_reserved1_MASK 0x00000100 629 #define MISC1_Y_RX_ERROR_STATUS_reserved1_ALIGN 0 630 #define MISC1_Y_RX_ERROR_STATUS_reserved1_BITS 1 631 #define MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT 8 632 633 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ 634 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 635 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 636 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 637 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 638 639 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved2 [06:05] */ 640 #define MISC1_Y_RX_ERROR_STATUS_reserved2_MASK 0x00000060 641 #define MISC1_Y_RX_ERROR_STATUS_reserved2_ALIGN 0 642 #define MISC1_Y_RX_ERROR_STATUS_reserved2_BITS 2 643 #define MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT 5 644 645 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ 646 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 647 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 648 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 649 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 650 651 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved3 [03:02] */ 652 #define MISC1_Y_RX_ERROR_STATUS_reserved3_MASK 0x0000000c 653 #define MISC1_Y_RX_ERROR_STATUS_reserved3_ALIGN 0 654 #define MISC1_Y_RX_ERROR_STATUS_reserved3_BITS 2 655 #define MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT 2 656 657 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ 658 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 659 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 660 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 661 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 662 663 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved4 [00:00] */ 664 #define MISC1_Y_RX_ERROR_STATUS_reserved4_MASK 0x00000001 665 #define MISC1_Y_RX_ERROR_STATUS_reserved4_ALIGN 0 666 #define MISC1_Y_RX_ERROR_STATUS_reserved4_BITS 1 667 #define MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT 0 668 669 670 /**************************************************************************** 671 * MISC1 :: UV_RX_ERROR_STATUS 672 ***************************************************************************/ 673 /* MISC1 :: UV_RX_ERROR_STATUS :: reserved0 [31:14] */ 674 #define MISC1_UV_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 675 #define MISC1_UV_RX_ERROR_STATUS_reserved0_ALIGN 0 676 #define MISC1_UV_RX_ERROR_STATUS_reserved0_BITS 18 677 #define MISC1_UV_RX_ERROR_STATUS_reserved0_SHIFT 14 678 679 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ 680 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 681 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 682 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 683 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 684 685 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ 686 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 687 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 688 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 689 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 690 691 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ 692 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 693 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 694 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 695 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 696 697 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ 698 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 699 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 700 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 701 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 702 703 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ 704 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 705 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 706 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 707 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 708 709 /* MISC1 :: UV_RX_ERROR_STATUS :: reserved1 [08:08] */ 710 #define MISC1_UV_RX_ERROR_STATUS_reserved1_MASK 0x00000100 711 #define MISC1_UV_RX_ERROR_STATUS_reserved1_ALIGN 0 712 #define MISC1_UV_RX_ERROR_STATUS_reserved1_BITS 1 713 #define MISC1_UV_RX_ERROR_STATUS_reserved1_SHIFT 8 714 715 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ 716 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 717 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 718 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 719 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 720 721 /* MISC1 :: UV_RX_ERROR_STATUS :: reserved2 [06:05] */ 722 #define MISC1_UV_RX_ERROR_STATUS_reserved2_MASK 0x00000060 723 #define MISC1_UV_RX_ERROR_STATUS_reserved2_ALIGN 0 724 #define MISC1_UV_RX_ERROR_STATUS_reserved2_BITS 2 725 #define MISC1_UV_RX_ERROR_STATUS_reserved2_SHIFT 5 726 727 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ 728 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 729 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 730 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 731 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 732 733 /* MISC1 :: UV_RX_ERROR_STATUS :: reserved3 [03:02] */ 734 #define MISC1_UV_RX_ERROR_STATUS_reserved3_MASK 0x0000000c 735 #define MISC1_UV_RX_ERROR_STATUS_reserved3_ALIGN 0 736 #define MISC1_UV_RX_ERROR_STATUS_reserved3_BITS 2 737 #define MISC1_UV_RX_ERROR_STATUS_reserved3_SHIFT 2 738 739 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ 740 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 741 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 742 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 743 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 744 745 /* MISC1 :: UV_RX_ERROR_STATUS :: reserved4 [00:00] */ 746 #define MISC1_UV_RX_ERROR_STATUS_reserved4_MASK 0x00000001 747 #define MISC1_UV_RX_ERROR_STATUS_reserved4_ALIGN 0 748 #define MISC1_UV_RX_ERROR_STATUS_reserved4_BITS 1 749 #define MISC1_UV_RX_ERROR_STATUS_reserved4_SHIFT 0 750 751 /**************************************************************************** 752 * Datatype Definitions. 753 ***************************************************************************/ 754 #endif /* #ifndef MACFILE_H__ */ 755 756 /* End of File */ 757 758