Searched refs:INREG (Results 1 – 11 of 11) sorted by relevance
338 if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13) in radeon_pm_enable_dynamic_mode()421 if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) in radeon_pm_enable_dynamic_mode()473 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) || in radeon_pm_enable_dynamic_mode()475 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) { in radeon_pm_enable_dynamic_mode()491 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) in radeon_pm_enable_dynamic_mode()502 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) { in radeon_pm_enable_dynamic_mode()558 return INREG( MC_IND_DATA); in INMC()573 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL); in radeon_pm_save_regs()574 rinfo->save_regs[10] = INREG(DISP_PWR_MAN); in radeon_pm_save_regs()575 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL); in radeon_pm_save_regs()[all …]
29 local_base = INREG(MC_FB_LOCATION) << 16; in radeon_fixup_offset()200 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); in radeonfb_engine_reset()211 host_path_cntl = INREG(HOST_PATH_CNTL); in radeonfb_engine_reset()212 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); in radeonfb_engine_reset()221 INREG(RBBM_SOFT_RESET); in radeonfb_engine_reset()223 tmp = INREG(RB2D_DSTCACHE_MODE); in radeonfb_engine_reset()234 INREG(RBBM_SOFT_RESET); in radeonfb_engine_reset()243 INREG(RBBM_SOFT_RESET); in radeonfb_engine_reset()247 INREG(HOST_PATH_CNTL); in radeonfb_engine_reset()268 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) | in radeonfb_engine_init()[all …]
23 val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN); in radeon_gpio_setscl()28 (void)INREG(chan->ddc_reg); in radeon_gpio_setscl()37 val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN); in radeon_gpio_setsda()42 (void)INREG(chan->ddc_reg); in radeon_gpio_setsda()51 val = INREG(chan->ddc_reg); in radeon_gpio_getscl()62 val = INREG(chan->ddc_reg); in radeon_gpio_getsda()156 (INREG(LVDS_GEN_CNTL) & LVDS_ON)) { in radeon_probe_i2c_connector()
310 temp = INREG(MPP_TB_CONFIG); in radeon_map_ROM()314 temp = INREG(MPP_TB_CONFIG); in radeon_map_ROM()478 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) in radeon_probe_pll_params()484 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0) in radeon_probe_pll_params()488 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) in radeon_probe_pll_params()504 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; in radeon_probe_pll_params()505 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1); in radeon_probe_pll_params()887 tmp = INREG(LVDS_GEN_CNTL); in radeonfb_ioctl()891 tmp = INREG(LVDS_GEN_CNTL); in radeonfb_ioctl()899 tmp = INREG(CRTC_EXT_CNTL); in radeonfb_ioctl()[all …]
393 #define INREG(addr) readl((rinfo->mmio_base)+addr) macro403 tmp = INREG(addr); in _OUTREGP()434 (void)INREG(CLOCK_CNTL_DATA); in radeon_pll_errata_after_index()435 (void)INREG(CRTC_GEN_CNTL); in radeon_pll_errata_after_index()446 save = INREG(CLOCK_CNTL_INDEX); in radeon_pll_errata_after_data()449 tmp = INREG(CLOCK_CNTL_DATA); in radeon_pll_errata_after_data()460 data = INREG(CLOCK_CNTL_DATA); in __INPLL()541 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) in _radeon_fifo_wait()563 if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) in radeon_engine_flush()579 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { in _radeon_engine_idle()
324 ulOrigCRTC_EXT_CNTL = INREG(CRTC_EXT_CNTL); in radeon_crt_is_connected()329 ulOrigDAC_EXT_CNTL = INREG(DAC_EXT_CNTL); in radeon_crt_is_connected()343 ulOrigDAC_CNTL = INREG(DAC_CNTL); in radeon_crt_is_connected()353 ulData = INREG(DAC_CNTL); in radeon_crt_is_connected()568 ((rinfo->bios_seg && (INREG(BIOS_4_SCRATCH) & 4)) in radeon_probe_screens()569 || (INREG(LVDS_GEN_CNTL) & LVDS_ON))) { in radeon_probe_screens()832 u32 tmp = INREG(FP_HORZ_STRETCH) & HORZ_PANEL_SIZE; in radeon_check_modes()834 tmp = INREG(FP_VERT_STRETCH) & VERT_PANEL_SIZE; in radeon_check_modes()
72 lvds_gen_cntl = INREG(LVDS_GEN_CNTL); in radeon_bl_update_status()
284 if (INREG(LVDS) & PORT_ENABLE) in intelfbhw_check_non_crt()286 if (INREG(DVOA) & PORT_ENABLE) in intelfbhw_check_non_crt()288 if (INREG(DVOB) & PORT_ENABLE) in intelfbhw_check_non_crt()290 if (INREG(DVOC) & PORT_ENABLE) in intelfbhw_check_non_crt()425 tmp = INREG(DSPACNTR); in intelfbhw_do_blank()432 tmp = INREG(DSPABASE); in intelfbhw_do_blank()449 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK; in intelfbhw_do_blank()529 hw->vga0_divisor = INREG(VGA0_DIVISOR); in intelfbhw_read_hw_state()530 hw->vga1_divisor = INREG(VGA1_DIVISOR); in intelfbhw_read_hw_state()531 hw->vga_pd = INREG(VGAPD); in intelfbhw_read_hw_state()[all …]
62 val = INREG(chan->reg); in intelfb_gpio_setscl()73 val = INREG(chan->reg); in intelfb_gpio_setsda()84 val = INREG(chan->reg); in intelfb_gpio_getscl()96 val = INREG(chan->reg); in intelfb_gpio_getsda()
525 #define INREG(addr) readl((u32 __iomem *)(dinfo->mmio_base + (addr))) macro553 head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \554 tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \
1373 OUTREG(DPLL_A, INREG(DPLL_A) & ~DPLL_VCO_ENABLE); in intelfb_set_par()1594 if (INREG(CURSOR_A_BASEADDR) != physical) { in intelfb_cursor()