1 /*
2 * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
3 * module (C) 2006 Tim Small
4 *
5 * This file may be distributed under the terms of the GNU General
6 * Public License.
7 *
8 * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
9 * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
10 * others.
11 *
12 * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
13 *
14 * Written with reference to 82443BX Host Bridge Datasheet:
15 * http://download.intel.com/design/chipsets/datashts/29063301.pdf
16 * references to this document given in [].
17 *
18 * This module doesn't support the 440LX, but it may be possible to
19 * make it do so (the 440LX's register definitions are different, but
20 * not completely so - I haven't studied them in enough detail to know
21 * how easy this would be).
22 */
23
24 #include <linux/module.h>
25 #include <linux/init.h>
26
27 #include <linux/pci.h>
28 #include <linux/pci_ids.h>
29
30
31 #include <linux/edac.h>
32 #include "edac_core.h"
33
34 #define I82443_REVISION "0.1"
35
36 #define EDAC_MOD_STR "i82443bxgx_edac"
37
38 /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
39 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
40 * rows" "The 82443BX supports multiple-bit error detection and
41 * single-bit error correction when ECC mode is enabled and
42 * single/multi-bit error detection when correction is disabled.
43 * During writes to the DRAM, the 82443BX generates ECC for the data
44 * on a QWord basis. Partial QWord writes require a read-modify-write
45 * cycle when ECC is enabled."
46 */
47
48 /* "Additionally, the 82443BX ensures that the data is corrected in
49 * main memory so that accumulation of errors is prevented. Another
50 * error within the same QWord would result in a double-bit error
51 * which is unrecoverable. This is known as hardware scrubbing since
52 * it requires no software intervention to correct the data in memory."
53 */
54
55 /* [Also see page 100 (section 4.3), "DRAM Interface"]
56 * [Also see page 112 (section 4.6.1.4), ECC]
57 */
58
59 #define I82443BXGX_NR_CSROWS 8
60 #define I82443BXGX_NR_CHANS 1
61 #define I82443BXGX_NR_DIMMS 4
62
63 /* 82443 PCI Device 0 */
64 #define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
65 * config space offset */
66 #define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
67 * row is non-ECC */
68 #define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
69
70 #define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
71 #define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
72 #define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
73 #define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
74 #define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
75
76 #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
77
78 /* 82443 PCI Device 0 */
79 #define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
80 * config space offset, Error Address
81 * Pointer Register */
82 #define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
83 #define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
84 #define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
85
86 #define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
87 * config space offset. */
88 #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
89 #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
90
91 #define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
92 * config space offset. */
93 #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
94 #define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
95 #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
96 #define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
97
98 #define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
99 * config space offset. */
100 #define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
101 #define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
102 #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
103 #define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
104
105 #define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
106 * config space offset. */
107
108 /* FIXME - don't poll when ECC disabled? */
109
110 struct i82443bxgx_edacmc_error_info {
111 u32 eap;
112 };
113
114 static struct edac_pci_ctl_info *i82443bxgx_pci;
115
116 static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
117 * already registered driver
118 */
119
120 static int i82443bxgx_registered = 1;
121
i82443bxgx_edacmc_get_error_info(struct mem_ctl_info * mci,struct i82443bxgx_edacmc_error_info * info)122 static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
123 struct i82443bxgx_edacmc_error_info
124 *info)
125 {
126 struct pci_dev *pdev;
127 pdev = to_pci_dev(mci->dev);
128 pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
129 if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
130 /* Clear error to allow next error to be reported [p.61] */
131 pci_write_bits32(pdev, I82443BXGX_EAP,
132 I82443BXGX_EAP_OFFSET_SBE,
133 I82443BXGX_EAP_OFFSET_SBE);
134
135 if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
136 /* Clear error to allow next error to be reported [p.61] */
137 pci_write_bits32(pdev, I82443BXGX_EAP,
138 I82443BXGX_EAP_OFFSET_MBE,
139 I82443BXGX_EAP_OFFSET_MBE);
140 }
141
i82443bxgx_edacmc_process_error_info(struct mem_ctl_info * mci,struct i82443bxgx_edacmc_error_info * info,int handle_errors)142 static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
143 struct
144 i82443bxgx_edacmc_error_info
145 *info, int handle_errors)
146 {
147 int error_found = 0;
148 u32 eapaddr, page, pageoffset;
149
150 /* bits 30:12 hold the 4kb block in which the error occurred
151 * [p.61] */
152 eapaddr = (info->eap & 0xfffff000);
153 page = eapaddr >> PAGE_SHIFT;
154 pageoffset = eapaddr - (page << PAGE_SHIFT);
155
156 if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
157 error_found = 1;
158 if (handle_errors)
159 edac_mc_handle_ce(mci, page, pageoffset,
160 /* 440BX/GX don't make syndrome information
161 * available */
162 0, edac_mc_find_csrow_by_page(mci, page), 0,
163 mci->ctl_name);
164 }
165
166 if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
167 error_found = 1;
168 if (handle_errors)
169 edac_mc_handle_ue(mci, page, pageoffset,
170 edac_mc_find_csrow_by_page(mci, page),
171 mci->ctl_name);
172 }
173
174 return error_found;
175 }
176
i82443bxgx_edacmc_check(struct mem_ctl_info * mci)177 static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
178 {
179 struct i82443bxgx_edacmc_error_info info;
180
181 debugf1("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__);
182 i82443bxgx_edacmc_get_error_info(mci, &info);
183 i82443bxgx_edacmc_process_error_info(mci, &info, 1);
184 }
185
i82443bxgx_init_csrows(struct mem_ctl_info * mci,struct pci_dev * pdev,enum edac_type edac_mode,enum mem_type mtype)186 static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
187 struct pci_dev *pdev,
188 enum edac_type edac_mode,
189 enum mem_type mtype)
190 {
191 struct csrow_info *csrow;
192 int index;
193 u8 drbar, dramc;
194 u32 row_base, row_high_limit, row_high_limit_last;
195
196 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
197 row_high_limit_last = 0;
198 for (index = 0; index < mci->nr_csrows; index++) {
199 csrow = &mci->csrows[index];
200 pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
201 debugf1("MC%d: %s: %s() Row=%d DRB = %#0x\n",
202 mci->mc_idx, __FILE__, __func__, index, drbar);
203 row_high_limit = ((u32) drbar << 23);
204 /* find the DRAM Chip Select Base address and mask */
205 debugf1("MC%d: %s: %s() Row=%d, "
206 "Boundary Address=%#0x, Last = %#0x\n",
207 mci->mc_idx, __FILE__, __func__, index, row_high_limit,
208 row_high_limit_last);
209
210 /* 440GX goes to 2GB, represented with a DRB of 0. */
211 if (row_high_limit_last && !row_high_limit)
212 row_high_limit = 1UL << 31;
213
214 /* This row is empty [p.49] */
215 if (row_high_limit == row_high_limit_last)
216 continue;
217 row_base = row_high_limit_last;
218 csrow->first_page = row_base >> PAGE_SHIFT;
219 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
220 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
221 /* EAP reports in 4kilobyte granularity [61] */
222 csrow->grain = 1 << 12;
223 csrow->mtype = mtype;
224 /* I don't think 440BX can tell you device type? FIXME? */
225 csrow->dtype = DEV_UNKNOWN;
226 /* Mode is global to all rows on 440BX */
227 csrow->edac_mode = edac_mode;
228 row_high_limit_last = row_high_limit;
229 }
230 }
231
i82443bxgx_edacmc_probe1(struct pci_dev * pdev,int dev_idx)232 static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
233 {
234 struct mem_ctl_info *mci;
235 u8 dramc;
236 u32 nbxcfg, ecc_mode;
237 enum mem_type mtype;
238 enum edac_type edac_mode;
239
240 debugf0("MC: %s: %s()\n", __FILE__, __func__);
241
242 /* Something is really hosed if PCI config space reads from
243 * the MC aren't working.
244 */
245 if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
246 return -EIO;
247
248 mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS, 0);
249
250 if (mci == NULL)
251 return -ENOMEM;
252
253 debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci);
254 mci->dev = &pdev->dev;
255 mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
256 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
257 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
258 switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
259 case I82443BXGX_DRAMC_DRAM_IS_EDO:
260 mtype = MEM_EDO;
261 break;
262 case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
263 mtype = MEM_SDR;
264 break;
265 case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
266 mtype = MEM_RDR;
267 break;
268 default:
269 debugf0("Unknown/reserved DRAM type value "
270 "in DRAMC register!\n");
271 mtype = -MEM_UNKNOWN;
272 }
273
274 if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
275 mci->edac_cap = mci->edac_ctl_cap;
276 else
277 mci->edac_cap = EDAC_FLAG_NONE;
278
279 mci->scrub_cap = SCRUB_FLAG_HW_SRC;
280 pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
281 ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
282 (BIT(0) | BIT(1)));
283
284 mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
285 ? SCRUB_HW_SRC : SCRUB_NONE;
286
287 switch (ecc_mode) {
288 case I82443BXGX_NBXCFG_INTEGRITY_NONE:
289 edac_mode = EDAC_NONE;
290 break;
291 case I82443BXGX_NBXCFG_INTEGRITY_EC:
292 edac_mode = EDAC_EC;
293 break;
294 case I82443BXGX_NBXCFG_INTEGRITY_ECC:
295 case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
296 edac_mode = EDAC_SECDED;
297 break;
298 default:
299 debugf0("%s(): Unknown/reserved ECC state "
300 "in NBXCFG register!\n", __func__);
301 edac_mode = EDAC_UNKNOWN;
302 break;
303 }
304
305 i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
306
307 /* Many BIOSes don't clear error flags on boot, so do this
308 * here, or we get "phantom" errors occurring at module-load
309 * time. */
310 pci_write_bits32(pdev, I82443BXGX_EAP,
311 (I82443BXGX_EAP_OFFSET_SBE |
312 I82443BXGX_EAP_OFFSET_MBE),
313 (I82443BXGX_EAP_OFFSET_SBE |
314 I82443BXGX_EAP_OFFSET_MBE));
315
316 mci->mod_name = EDAC_MOD_STR;
317 mci->mod_ver = I82443_REVISION;
318 mci->ctl_name = "I82443BXGX";
319 mci->dev_name = pci_name(pdev);
320 mci->edac_check = i82443bxgx_edacmc_check;
321 mci->ctl_page_to_phys = NULL;
322
323 if (edac_mc_add_mc(mci)) {
324 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
325 goto fail;
326 }
327
328 /* allocating generic PCI control info */
329 i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
330 if (!i82443bxgx_pci) {
331 printk(KERN_WARNING
332 "%s(): Unable to create PCI control\n",
333 __func__);
334 printk(KERN_WARNING
335 "%s(): PCI error report via EDAC not setup\n",
336 __func__);
337 }
338
339 debugf3("MC: %s: %s(): success\n", __FILE__, __func__);
340 return 0;
341
342 fail:
343 edac_mc_free(mci);
344 return -ENODEV;
345 }
346
347 EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1);
348
349 /* returns count (>= 0), or negative on error */
i82443bxgx_edacmc_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)350 static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
351 const struct pci_device_id *ent)
352 {
353 int rc;
354
355 debugf0("MC: %s: %s()\n", __FILE__, __func__);
356
357 /* don't need to call pci_enable_device() */
358 rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
359
360 if (mci_pdev == NULL)
361 mci_pdev = pci_dev_get(pdev);
362
363 return rc;
364 }
365
i82443bxgx_edacmc_remove_one(struct pci_dev * pdev)366 static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
367 {
368 struct mem_ctl_info *mci;
369
370 debugf0("%s: %s()\n", __FILE__, __func__);
371
372 if (i82443bxgx_pci)
373 edac_pci_release_generic_ctl(i82443bxgx_pci);
374
375 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
376 return;
377
378 edac_mc_free(mci);
379 }
380
381 EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
382
383 static DEFINE_PCI_DEVICE_TABLE(i82443bxgx_pci_tbl) = {
384 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
385 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
386 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
387 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
388 {0,} /* 0 terminated list. */
389 };
390
391 MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
392
393 static struct pci_driver i82443bxgx_edacmc_driver = {
394 .name = EDAC_MOD_STR,
395 .probe = i82443bxgx_edacmc_init_one,
396 .remove = __devexit_p(i82443bxgx_edacmc_remove_one),
397 .id_table = i82443bxgx_pci_tbl,
398 };
399
i82443bxgx_edacmc_init(void)400 static int __init i82443bxgx_edacmc_init(void)
401 {
402 int pci_rc;
403 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
404 opstate_init();
405
406 pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
407 if (pci_rc < 0)
408 goto fail0;
409
410 if (mci_pdev == NULL) {
411 const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
412 int i = 0;
413 i82443bxgx_registered = 0;
414
415 while (mci_pdev == NULL && id->vendor != 0) {
416 mci_pdev = pci_get_device(id->vendor,
417 id->device, NULL);
418 i++;
419 id = &i82443bxgx_pci_tbl[i];
420 }
421 if (!mci_pdev) {
422 debugf0("i82443bxgx pci_get_device fail\n");
423 pci_rc = -ENODEV;
424 goto fail1;
425 }
426
427 pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
428
429 if (pci_rc < 0) {
430 debugf0("i82443bxgx init fail\n");
431 pci_rc = -ENODEV;
432 goto fail1;
433 }
434 }
435
436 return 0;
437
438 fail1:
439 pci_unregister_driver(&i82443bxgx_edacmc_driver);
440
441 fail0:
442 if (mci_pdev != NULL)
443 pci_dev_put(mci_pdev);
444
445 return pci_rc;
446 }
447
i82443bxgx_edacmc_exit(void)448 static void __exit i82443bxgx_edacmc_exit(void)
449 {
450 pci_unregister_driver(&i82443bxgx_edacmc_driver);
451
452 if (!i82443bxgx_registered)
453 i82443bxgx_edacmc_remove_one(mci_pdev);
454
455 if (mci_pdev)
456 pci_dev_put(mci_pdev);
457 }
458
459 module_init(i82443bxgx_edacmc_init);
460 module_exit(i82443bxgx_edacmc_exit);
461
462 MODULE_LICENSE("GPL");
463 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
464 MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
465
466 module_param(edac_op_state, int, 0444);
467 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
468