Searched refs:HDLC_ENCODING_DIFF_BIPHASE_LEVEL (Results 1 – 4 of 4) sorted by relevance
109 #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7 macro
4312 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4385 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4444 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: in sync_mode()
4758 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break; in usc_set_sdlc_mode()4833 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break; in usc_set_sdlc_mode()5010 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break; in usc_set_sdlc_mode()
4581 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */ in hdlc_mode()