1 /* 2 * arch/arm/plat-omap/include/mach/fpga.h 3 * 4 * Interrupt handler for OMAP-1510 FPGA 5 * 6 * Copyright (C) 2001 RidgeRun, Inc. 7 * Author: Greg Lonnon <glonnon@ridgerun.com> 8 * 9 * Copyright (C) 2002 MontaVista Software, Inc. 10 * 11 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 12 * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 19 #ifndef __ASM_ARCH_OMAP_FPGA_H 20 #define __ASM_ARCH_OMAP_FPGA_H 21 22 extern void omap1510_fpga_init_irq(void); 23 24 #define fpga_read(reg) __raw_readb(reg) 25 #define fpga_write(val, reg) __raw_writeb(val, reg) 26 27 /* 28 * --------------------------------------------------------------------------- 29 * H2/P2 Debug board FPGA 30 * --------------------------------------------------------------------------- 31 */ 32 /* maps in the FPGA registers and the ETHR registers */ 33 #define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ 34 #define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ 35 #define H2P2_DBG_FPGA_START 0x04000000 /* PA */ 36 37 #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) 38 #define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ 39 #define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ 40 #define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ 41 #define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ 42 #define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ 43 #define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ 44 #define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ 45 46 /* NOTE: most boards don't have a static mapping for the FPGA ... */ 47 struct h2p2_dbg_fpga { 48 /* offset 0x00 */ 49 u16 smc91x[8]; 50 /* offset 0x10 */ 51 u16 fpga_rev; 52 u16 board_rev; 53 u16 gpio_outputs; 54 u16 leds; 55 /* offset 0x18 */ 56 u16 misc_inputs; 57 u16 lan_status; 58 u16 lan_reset; 59 u16 reserved0; 60 /* offset 0x20 */ 61 u16 ps2_data; 62 u16 ps2_ctrl; 63 /* plus also 4 rs232 ports ... */ 64 }; 65 66 /* LEDs definition on debug board (16 LEDs, all physically green) */ 67 #define H2P2_DBG_FPGA_LED_GREEN (1 << 15) 68 #define H2P2_DBG_FPGA_LED_AMBER (1 << 14) 69 #define H2P2_DBG_FPGA_LED_RED (1 << 13) 70 #define H2P2_DBG_FPGA_LED_BLUE (1 << 12) 71 /* cpu0 load-meter LEDs */ 72 #define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... 73 #define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 74 #define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) 75 76 #define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) 77 #define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) 78 79 /* 80 * --------------------------------------------------------------------------- 81 * OMAP-1510 FPGA 82 * --------------------------------------------------------------------------- 83 */ 84 #define OMAP1510_FPGA_BASE 0xE8000000 /* VA */ 85 #define OMAP1510_FPGA_SIZE SZ_4K 86 #define OMAP1510_FPGA_START 0x08000000 /* PA */ 87 88 /* Revision */ 89 #define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0) 90 #define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1) 91 92 #define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2) 93 #define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3) 94 #define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4) 95 #define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5) 96 97 /* Interrupt status */ 98 #define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6) 99 #define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7) 100 101 /* Interrupt mask */ 102 #define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8) 103 #define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9) 104 105 /* Reset registers */ 106 #define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa) 107 #define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb) 108 109 #define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc) 110 #define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe) 111 #define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf) 112 #define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14) 113 #define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15) 114 #define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16) 115 #define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18) 116 #define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100) 117 #define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101) 118 #define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102) 119 120 #define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204) 121 122 #define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205) 123 #define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206) 124 #define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207) 125 #define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208) 126 #define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209) 127 #define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a) 128 #define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b) 129 #define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c) 130 #define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d) 131 #define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e) 132 #define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210) 133 134 #define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) 135 136 /* 137 * Power up Giga UART driver, turn on HID clock. 138 * Turn off BT power, since we're not using it and it 139 * draws power. 140 */ 141 #define OMAP1510_FPGA_RESET_VALUE 0x42 142 143 #define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) 144 #define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) 145 #define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) 146 #define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) 147 #define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) 148 #define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) 149 #define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) 150 #define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) 151 152 /* 153 * Innovator/OMAP1510 FPGA HID register bit definitions 154 */ 155 #define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */ 156 #define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */ 157 #define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ 158 #define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ 159 #define OMAP1510_FPGA_HID_MISO (1<<4) /* input */ 160 #define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ 161 #define OMAP1510_FPGA_HID_rsrvd (1<<6) 162 #define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ 163 164 /* The FPGA IRQ is cascaded through GPIO_13 */ 165 #define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) 166 167 /* IRQ Numbers for interrupts muxed through the FPGA */ 168 #define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0) 169 #define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1) 170 #define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2) 171 #define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3) 172 #define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4) 173 #define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5) 174 #define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6) 175 #define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7) 176 #define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8) 177 #define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9) 178 #define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10) 179 #define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11) 180 #define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12) 181 #define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13) 182 #define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14) 183 #define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15) 184 #define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16) 185 #define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17) 186 #define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18) 187 #define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19) 188 #define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20) 189 #define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21) 190 #define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22) 191 #define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23) 192 193 #endif 194