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Searched refs:Fld (Results 1 – 7 of 7) sorted by relevance

/linux-3.4.99/drivers/video/mbx/
Dreg_bits.h6 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro
16 #define SYSCLKSRC_SEL Fld(2,0)
22 #define PIXCLKSRC_SEL Fld(2,0)
31 #define CORE_PLL_M Fld(6,7)
33 #define CORE_PLL_N Fld(3,4)
35 #define CORE_PLL_P Fld(3,1)
40 #define DISP_PLL_M Fld(6,7)
42 #define DISP_PLL_N Fld(3,4)
44 #define DISP_PLL_P Fld(3,1)
64 #define MBXCLK_DIV Fld(2,2)
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/linux-3.4.99/arch/arm/mach-sa1100/include/mach/
DSA-1101.h101 #define SMCR_DCAC Fld(2,0) /* Number of column address bits */
102 #define SMCR_DRAC Fld(2,2) /* Number of row address bits */
104 #define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */
111 #define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */
112 #define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */
114 #define SNPR_BankSelect Fld(2,27) /* Bank select */
145 #define VMCCR_RefPeriod Fld(2,3) /* Refresh period */
146 #define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */
149 #define VMCCR_RefLow Fld(6,11) /* refresh low counter */
150 #define VMCCR_RefHigh Fld(7,17) /* refresh high counter */
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DSA-1100.h136 #define UDCAR_ADD Fld (7, 0) /* function ADDress */
138 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
144 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
176 #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
178 #define UDCWC_WC Fld (4, 0) /* Write Count */
180 #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
336 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
337 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
377 #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
473 #define SDCR2_AMV Fld (8, 0) /* Address Match Value */
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Dbitfield.h46 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro
/linux-3.4.99/arch/arm/mach-pxa/include/mach/
Dregs-lcd.h88 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
91 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
94 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
97 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
100 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
103 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */
106 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
109 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
125 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
128 #define LCCR3_ACB Fld (8, 8) /* AC Bias */
Dbitfield.h46 #define Fld(Size, Shft) (((Size) << 16) + (Shft)) macro
/linux-3.4.99/arch/arm/include/asm/hardware/
Dsa1111.h93 #define SMCR_DRAC Fld(3, 2)