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Searched refs:EXYNOS5_CLKSRC_TOP0 (Results 1 – 2 of 2) sorted by relevance

/linux-3.4.99/arch/arm/mach-exynos/
Dclock-exynos5.c380 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
399 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
408 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
425 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
890 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
/linux-3.4.99/arch/arm/mach-exynos/include/mach/
Dregs-clock.h281 #define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210) macro