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Searched refs:EXYNOS4_VPLL_CON0 (Results 1 – 3 of 3) sorted by relevance

/linux-3.4.99/arch/arm/mach-exynos/
Dpm.c62 SAVE_ITEM(EXYNOS4_VPLL_CON0),
269 pll_con = __raw_readl(EXYNOS4_VPLL_CON0); in exynos4_restore_pll()
Dclock-exynos4.c1392 vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0); in exynos4_vpll_set_rate()
1422 __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0); in exynos4_vpll_set_rate()
1426 while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT))) in exynos4_vpll_set_rate()
1477 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), in exynos4_setup_clocks()
1486 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), in exynos4_setup_clocks()
/linux-3.4.99/arch/arm/mach-exynos/include/mach/
Dregs-clock.h34 #define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120) macro