1 /*
2  *  Copyright (C) NEC Electronics Corporation 2005-2006
3  *
4  *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
5  *          Copyright 2001 MontaVista Software Inc.
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License as published by
9  *  the Free Software Foundation; either version 2 of the License, or
10  *  (at your option) any later version.
11  *
12  *  This program is distributed in the hope that it will be useful,
13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *  GNU General Public License for more details.
16  *
17  *  You should have received a copy of the GNU General Public License
18  *  along with this program; if not, write to the Free Software
19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 #ifndef __ASM_EMMA_EMMA2RH_H
22 #define __ASM_EMMA_EMMA2RH_H
23 
24 #include <irq.h>
25 
26 /*
27  * EMMA2RH registers
28  */
29 #define REGBASE 0x10000000
30 
31 #define EMMA2RH_BHIF_STRAP_0	(0x000010+REGBASE)
32 #define EMMA2RH_BHIF_INT_ST_0	(0x000030+REGBASE)
33 #define EMMA2RH_BHIF_INT_ST_1	(0x000034+REGBASE)
34 #define EMMA2RH_BHIF_INT_ST_2	(0x000038+REGBASE)
35 #define EMMA2RH_BHIF_INT_EN_0	(0x000040+REGBASE)
36 #define EMMA2RH_BHIF_INT_EN_1	(0x000044+REGBASE)
37 #define EMMA2RH_BHIF_INT_EN_2	(0x000048+REGBASE)
38 #define EMMA2RH_BHIF_INT1_EN_0	(0x000050+REGBASE)
39 #define EMMA2RH_BHIF_INT1_EN_1	(0x000054+REGBASE)
40 #define EMMA2RH_BHIF_INT1_EN_2	(0x000058+REGBASE)
41 #define EMMA2RH_BHIF_SW_INT	(0x000070+REGBASE)
42 #define EMMA2RH_BHIF_SW_INT_EN	(0x000080+REGBASE)
43 #define EMMA2RH_BHIF_SW_INT_CLR	(0x000090+REGBASE)
44 #define EMMA2RH_BHIF_MAIN_CTRL	(0x0000b4+REGBASE)
45 #define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS	(0x0000c0+REGBASE)
46 #define EMMA2RH_GPIO_DIR	(0x110d20+REGBASE)
47 #define EMMA2RH_GPIO_INT_ST	(0x110d30+REGBASE)
48 #define EMMA2RH_GPIO_INT_MASK	(0x110d3c+REGBASE)
49 #define EMMA2RH_GPIO_INT_MODE	(0x110d48+REGBASE)
50 #define EMMA2RH_GPIO_INT_CND_A	(0x110d54+REGBASE)
51 #define EMMA2RH_GPIO_INT_CND_B	(0x110d60+REGBASE)
52 #define EMMA2RH_PBRD_INT_EN	(0x100010+REGBASE)
53 #define EMMA2RH_PBRD_CLKSEL	(0x100028+REGBASE)
54 #define EMMA2RH_PFUR0_BASE	(0x101000+REGBASE)
55 #define EMMA2RH_PFUR1_BASE	(0x102000+REGBASE)
56 #define EMMA2RH_PFUR2_BASE	(0x103000+REGBASE)
57 #define EMMA2RH_PIIC0_BASE	(0x107000+REGBASE)
58 #define EMMA2RH_PIIC1_BASE	(0x108000+REGBASE)
59 #define EMMA2RH_PIIC2_BASE	(0x109000+REGBASE)
60 #define EMMA2RH_PCI_CONTROL	(0x200000+REGBASE)
61 #define EMMA2RH_PCI_ARBIT_CTR	(0x200004+REGBASE)
62 #define EMMA2RH_PCI_IWIN0_CTR	(0x200010+REGBASE)
63 #define EMMA2RH_PCI_IWIN1_CTR	(0x200014+REGBASE)
64 #define EMMA2RH_PCI_INIT_ESWP	(0x200018+REGBASE)
65 #define EMMA2RH_PCI_INT		(0x200020+REGBASE)
66 #define EMMA2RH_PCI_INT_EN	(0x200024+REGBASE)
67 #define EMMA2RH_PCI_TWIN_CTR	(0x200030+REGBASE)
68 #define EMMA2RH_PCI_TWIN_BADR	(0x200034+REGBASE)
69 #define EMMA2RH_PCI_TWIN0_DADR	(0x200038+REGBASE)
70 #define EMMA2RH_PCI_TWIN1_DADR	(0x20003c+REGBASE)
71 
72 /*
73  *  Memory map (physical address)
74  *
75  *  Note most of the following address must be properly aligned by the
76  *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
77  *  PCI_IO_BASE must be aligned along 16MB boundary.
78  */
79 
80 /* the actual ram size is detected at run-time */
81 #define EMMA2RH_RAM_BASE	0x00000000
82 #define EMMA2RH_RAM_SIZE	0x10000000	/* less than 256MB */
83 
84 #define EMMA2RH_IO_BASE		0x10000000
85 #define EMMA2RH_IO_SIZE		0x01000000	/* 16 MB */
86 
87 #define EMMA2RH_GENERALIO_BASE	0x11000000
88 #define EMMA2RH_GENERALIO_SIZE	0x01000000	/* 16 MB */
89 
90 #define EMMA2RH_PCI_IO_BASE	0x12000000
91 #define EMMA2RH_PCI_IO_SIZE	0x02000000	/* 32 MB */
92 
93 #define EMMA2RH_PCI_MEM_BASE	0x14000000
94 #define EMMA2RH_PCI_MEM_SIZE	0x08000000	/* 128 MB */
95 
96 #define EMMA2RH_ROM_BASE	0x1c000000
97 #define EMMA2RH_ROM_SIZE	0x04000000	/* 64 MB */
98 
99 #define EMMA2RH_PCI_CONFIG_BASE	EMMA2RH_PCI_IO_BASE
100 #define EMMA2RH_PCI_CONFIG_SIZE	EMMA2RH_PCI_IO_SIZE
101 
102 #define NUM_EMMA2RH_IRQ		96
103 
104 #define EMMA2RH_IRQ_BASE	(MIPS_CPU_IRQ_BASE + 8)
105 
106 /*
107  * emma2rh irq defs
108  */
109 
110 #define EMMA2RH_IRQ_INT(n)	(EMMA2RH_IRQ_BASE + (n))
111 
112 #define EMMA2RH_IRQ_PFUR0	EMMA2RH_IRQ_INT(49)
113 #define EMMA2RH_IRQ_PFUR1	EMMA2RH_IRQ_INT(50)
114 #define EMMA2RH_IRQ_PFUR2	EMMA2RH_IRQ_INT(51)
115 #define EMMA2RH_IRQ_PIIC0	EMMA2RH_IRQ_INT(56)
116 #define EMMA2RH_IRQ_PIIC1	EMMA2RH_IRQ_INT(57)
117 #define EMMA2RH_IRQ_PIIC2	EMMA2RH_IRQ_INT(58)
118 
119 /*
120  *  EMMA2RH Register Access
121  */
122 
123 #define EMMA2RH_BASE (0xa0000000)
124 
emma2rh_sync(void)125 static inline void emma2rh_sync(void)
126 {
127 	volatile u32 *p = (volatile u32 *)0xbfc00000;
128 	(void)(*p);
129 }
130 
emma2rh_out32(u32 offset,u32 val)131 static inline void emma2rh_out32(u32 offset, u32 val)
132 {
133 	*(volatile u32 *)(EMMA2RH_BASE | offset) = val;
134 	emma2rh_sync();
135 }
136 
emma2rh_in32(u32 offset)137 static inline u32 emma2rh_in32(u32 offset)
138 {
139 	u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
140 	return val;
141 }
142 
emma2rh_out16(u32 offset,u16 val)143 static inline void emma2rh_out16(u32 offset, u16 val)
144 {
145 	*(volatile u16 *)(EMMA2RH_BASE | offset) = val;
146 	emma2rh_sync();
147 }
148 
emma2rh_in16(u32 offset)149 static inline u16 emma2rh_in16(u32 offset)
150 {
151 	u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
152 	return val;
153 }
154 
emma2rh_out8(u32 offset,u8 val)155 static inline void emma2rh_out8(u32 offset, u8 val)
156 {
157 	*(volatile u8 *)(EMMA2RH_BASE | offset) = val;
158 	emma2rh_sync();
159 }
160 
emma2rh_in8(u32 offset)161 static inline u8 emma2rh_in8(u32 offset)
162 {
163 	u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
164 	return val;
165 }
166 
167 /**
168  * IIC registers map
169  **/
170 
171 /*---------------------------------------------------------------------------*/
172 /* CNT - Control register (00H R/W)                                          */
173 /*---------------------------------------------------------------------------*/
174 #define SPT         0x00000001
175 #define STT         0x00000002
176 #define ACKE        0x00000004
177 #define WTIM        0x00000008
178 #define SPIE        0x00000010
179 #define WREL        0x00000020
180 #define LREL        0x00000040
181 #define IICE        0x00000080
182 #define CNT_RESERVED    0x000000ff	/* reserved bit 0 */
183 
184 #define I2C_EMMA_START      (IICE | STT)
185 #define I2C_EMMA_STOP       (IICE | SPT)
186 #define I2C_EMMA_REPSTART   I2C_EMMA_START
187 
188 /*---------------------------------------------------------------------------*/
189 /* STA - Status register (10H Read)                                          */
190 /*---------------------------------------------------------------------------*/
191 #define MSTS        0x00000080
192 #define ALD         0x00000040
193 #define EXC         0x00000020
194 #define COI         0x00000010
195 #define TRC         0x00000008
196 #define ACKD        0x00000004
197 #define STD         0x00000002
198 #define SPD         0x00000001
199 
200 /*---------------------------------------------------------------------------*/
201 /* CSEL - Clock select register (20H R/W)                                    */
202 /*---------------------------------------------------------------------------*/
203 #define FCL         0x00000080
204 #define ND50        0x00000040
205 #define CLD         0x00000020
206 #define DAD         0x00000010
207 #define SMC         0x00000008
208 #define DFC         0x00000004
209 #define CL          0x00000003
210 #define CSEL_RESERVED   0x000000ff	/* reserved bit 0 */
211 
212 #define FAST397     0x0000008b
213 #define FAST297     0x0000008a
214 #define FAST347     0x0000000b
215 #define FAST260     0x0000000a
216 #define FAST130     0x00000008
217 #define STANDARD108 0x00000083
218 #define STANDARD83  0x00000082
219 #define STANDARD95  0x00000003
220 #define STANDARD73  0x00000002
221 #define STANDARD36  0x00000001
222 #define STANDARD71  0x00000000
223 
224 /*---------------------------------------------------------------------------*/
225 /* SVA - Slave address register (30H R/W)                                    */
226 /*---------------------------------------------------------------------------*/
227 #define SVA         0x000000fe
228 
229 /*---------------------------------------------------------------------------*/
230 /* SHR - Shift register (40H R/W)                                            */
231 /*---------------------------------------------------------------------------*/
232 #define SR          0x000000ff
233 
234 /*---------------------------------------------------------------------------*/
235 /* INT - Interrupt register (50H R/W)                                        */
236 /* INTM - Interrupt mask register (60H R/W)                                  */
237 /*---------------------------------------------------------------------------*/
238 #define INTE0       0x00000001
239 
240 /***********************************************************************
241  * I2C registers
242  ***********************************************************************
243  */
244 #define I2C_EMMA_CNT            0x00
245 #define I2C_EMMA_STA            0x10
246 #define I2C_EMMA_CSEL           0x20
247 #define I2C_EMMA_SVA            0x30
248 #define I2C_EMMA_SHR            0x40
249 #define I2C_EMMA_INT            0x50
250 #define I2C_EMMA_INTM           0x60
251 
252 /*
253  * include the board dependent part
254  */
255 #ifdef CONFIG_NEC_MARKEINS
256 #include <asm/emma/markeins.h>
257 #else
258 #error "Unknown EMMA2RH board!"
259 #endif
260 
261 #endif /* __ASM_EMMA_EMMA2RH_H */
262