Searched refs:DSPACNTR (Results 1 – 11 of 11) sorted by relevance
/linux-3.4.99/drivers/video/intelfb/ |
D | intelfbhw.c | 425 tmp = INREG(DSPACNTR); in intelfbhw_do_blank() 430 OUTREG(DSPACNTR, tmp); in intelfbhw_do_blank() 613 hw->disp_a_ctrl = INREG(DSPACNTR); in intelfbhw_read_hw_state() 1378 tmp = INREG(DSPACNTR); in intelfbhw_program_mode() 1380 OUTREG(DSPACNTR, tmp); in intelfbhw_program_mode() 1460 tmp = INREG(DSPACNTR); in intelfbhw_program_mode() 1463 OUTREG(DSPACNTR, tmp); in intelfbhw_program_mode() 1464 OUTREG(DSPACNTR, in intelfbhw_program_mode() 1470 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE); in intelfbhw_program_mode() 1476 tmp = INREG(DSPACNTR); in intelfbhw_program_mode() [all …]
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D | intelfbhw.h | 392 #define DSPACNTR 0x70180 macro
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/linux-3.4.99/drivers/gpu/drm/gma500/ |
D | oaktrail_crtc.c | 168 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; in oaktrail_crtc_dpms() 297 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; in oaktrail_crtc_mode_set() 520 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; in oaktrail_pipe_set_base()
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D | oaktrail_device.c | 216 regs->psb.saveDSPACNTR = PSB_RVDC32(DSPACNTR); in oaktrail_save_display_registers() 275 PSB_WVDC32(0x58000000, DSPACNTR); in oaktrail_save_display_registers() 350 PSB_WVDC32(regs->psb.saveDSPACNTR, DSPACNTR); in oaktrail_restore_display_registers()
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D | mdfld_intel_display.c | 155 int dspcntr_reg = DSPACNTR; in mdfld__intel_plane_set_alpha() 200 int dspcntr_reg = DSPACNTR; in mdfld__intel_pipe_set_base() 285 int dspcntr_reg = DSPACNTR; in mdfld_disable_crtc() 377 int dspcntr_reg = DSPACNTR; in mdfld_crtc_dpms() 769 int dspcntr_reg = DSPACNTR; in mdfld_crtc_mode_set()
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D | cdv_intel_display.c | 490 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; in cdv_intel_pipe_set_base() 568 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; in cdv_intel_crtc_dpms() 716 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; in cdv_intel_crtc_mode_set() 978 crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR); in cdv_intel_crtc_save() 1044 REG_READ(pipeA ? DSPACNTR : DSPBCNTR), in cdv_intel_crtc_restore() 1119 REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR); in cdv_intel_crtc_restore()
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D | psb_intel_display.c | 348 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; in psb_intel_pipe_set_base() 432 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; in psb_intel_crtc_dpms() 597 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; in psb_intel_crtc_mode_set() 870 crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR); in psb_intel_crtc_save() 949 REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR); in psb_intel_crtc_restore()
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D | mdfld_dsi_dpi.c | 121 u32 dspcntr_reg = DSPACNTR; in dsi_set_pipe_plane_enable_state() 826 u32 dspcntr_reg = DSPACNTR; in mdfld_dsi_dpi_mode_set() 876 REG_WRITE(DSPACNTR, 0x98000000); in mdfld_dsi_dpi_mode_set()
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D | mdfld_device.c | 190 u32 dspcntr_reg = DSPACNTR; in mdfld_save_display_registers() 383 u32 dspcntr_reg = DSPACNTR; in mdfld_restore_display_registers()
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D | mdfld_dsi_pkg_sender.c | 637 pkg_sender->dspcntr_reg = DSPACNTR; in mdfld_dsi_pkg_sender_init()
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D | psb_intel_reg.h | 580 #define DSPACNTR 0x70180 macro
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