Searched refs:DPLL_SYNCLOCK_ENABLE (Results 1 – 5 of 5) sorted by relevance
319 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { in cdv_restore_display_registers()320 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()325 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { in cdv_restore_display_registers()326 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
231 if ((REG_READ(dpll_reg) & DPLL_SYNCLOCK_ENABLE) == 0) { in cdv_dpll_set_clock_cdv()784 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()806 REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
209 #define DPLL_SYNCLOCK_ENABLE (1 << 29) macro
151 #define DPLL_SYNCLOCK_ENABLE (1 << 29) macro
831 #define DPLL_SYNCLOCK_ENABLE (1 << 29) macro