Searched refs:DPLL_FPA01_P1_POST_DIV_SHIFT (Results 1 – 5 of 5) sorted by relevance
232 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro
1341 DPLL_FPA01_P1_POST_DIV_SHIFT); in cdv_intel_crtc_clock_get()1361 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in cdv_intel_crtc_clock_get()
1159 DPLL_FPA01_P1_POST_DIV_SHIFT); in psb_intel_crtc_clock_get()1175 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in psb_intel_crtc_clock_get()
5262 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_crtc_mode_set()5284 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_crtc_mode_set()5289 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_crtc_mode_set()5875 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ironlake_crtc_mode_set()6911 DPLL_FPA01_P1_POST_DIV_SHIFT); in intel_crtc_clock_get()6935 DPLL_FPA01_P1_POST_DIV_SHIFT); in intel_crtc_clock_get()6949 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; in intel_crtc_clock_get()
867 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 macro