Searched refs:DMA10_IRQ_STATUS (Results 1 – 10 of 10) sorted by relevance
370 #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ macro
669 #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)670 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
686 #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)687 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
346 #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register … macro
648 #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)649 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val)
475 #define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */ macro
768 #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)769 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
376 #define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register … macro
617 #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)618 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)