Home
last modified time | relevance | path

Searched refs:DIV_U71_IDLE (Results 1 – 2 of 2) sorted by relevance

/linux-3.4.99/arch/arm/mach-tegra/
Dclock.h51 #define DIV_U71_IDLE (1 << 22) macro
Dtegra30_clocks.c1450 if (c->flags & DIV_U71_IDLE) { in tegra30_periph_clk_init()
2938 …58, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL…
2939 …b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL…
2940 … NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),