/linux-3.4.99/drivers/video/ |
D | platinumfb.h | 70 #define DIV4 0x40 macro 169 {{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }} 181 {{ 122, 7 + DIV4 }, { 62, 9 + DIV2 }} 193 {{ 26, 0 + DIV4 }, { 42, 6 + DIV2 }} 205 {{ 54, 3 + DIV4 }, { 95, 1 + DIV8 }} 217 {{ 54, 3 + DIV4 }, { 88, 1 + DIV8 }} 241 {{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }} 253 {{ 99, 4 + DIV8 }, { 42, 5 + DIV4 }} 265 {{ 26, 0 + DIV8 }, { 14, 2 + DIV4 }}
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/linux-3.4.99/arch/sh/kernel/cpu/sh4a/ |
D | clock-sh7785.c | 69 #define DIV4(_bit, _mask, _flags) \ macro 73 [DIV4_P] = DIV4(0, 0x0f80, 0), 74 [DIV4_DU] = DIV4(4, 0x0ff0, 0), 75 [DIV4_GA] = DIV4(8, 0x0030, 0), 76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), 77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), 78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), 79 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT), 80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
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D | clock-shx3.c | 64 #define DIV4(_bit, _mask, _flags) \ macro 68 [DIV4_P] = DIV4(0, 0x0f80, 0), 69 [DIV4_SHA] = DIV4(4, 0x0ff0, 0), 70 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), 71 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), 72 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), 73 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
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D | clock-sh7722.c | 120 #define DIV4(_reg, _bit, _mask, _flags) \ macro 126 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 127 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 128 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 129 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 130 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 131 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), 137 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0), 143 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), 144 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
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D | clock-sh7723.c | 123 #define DIV4(_reg, _bit, _mask, _flags) \ macro 127 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), 128 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), 129 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), 130 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), 131 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), 132 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0), 138 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0), 144 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0), 145 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
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D | clock-sh7366.c | 120 #define DIV4(_reg, _bit, _mask, _flags) \ macro 124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 129 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), 130 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), 131 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
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D | clock-sh7786.c | 70 #define DIV4(_bit, _mask, _flags) \ macro 74 [DIV4_P] = DIV4(0, 0x0b40, 0), 75 [DIV4_DU] = DIV4(4, 0x0010, 0), 76 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT), 77 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT), 78 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT), 79 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
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D | clock-sh7343.c | 117 #define DIV4(_reg, _bit, _mask, _flags) \ macro 121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), 122 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 126 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), 127 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), 128 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
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D | clock-sh7757.c | 65 #define DIV4(_bit, _mask, _flags) \ macro 73 [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT), 74 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT), 75 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
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D | clock-sh7724.c | 162 #define DIV4(_reg, _bit, _mask, _flags) \ macro 166 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 167 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 168 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 169 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0), 170 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
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/linux-3.4.99/arch/arm/mach-shmobile/ |
D | clock-sh7367.c | 179 #define DIV4(_reg, _bit, _mask, _flags) \ macro 183 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT), 184 [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT), 185 [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT), 186 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT), 187 [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0), 188 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0), 189 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0), 190 [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0), 191 [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0), [all …]
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D | clock-sh7377.c | 189 #define DIV4(_reg, _bit, _mask, _flags) \ macro 193 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT), 194 [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT), 195 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT), 196 [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT), 197 [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0), 198 [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0), 199 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0), 200 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0), 201 [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0), [all …]
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D | clock-sh7372.c | 349 #define DIV4(_reg, _bit, _mask, _flags) \ macro 353 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), 354 [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), 355 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), 356 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), 357 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), 358 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0), 359 [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0), 360 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), 361 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), [all …]
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D | clock-sh73a0.c | 263 #define DIV4(_reg, _bit, _mask, _flags) \ macro 267 [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT), 268 [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT), 269 [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT), 270 [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT), 271 [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0), 272 [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0), 273 [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0), 274 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0), 275 [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0), [all …]
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