Searched refs:DCSR (Results 1 – 13 of 13) sorted by relevance
2 Debug Control and Status Register (DCSR) Binding16 defined DCSR Memory Map. Child nodes will describe the individual25 The DCSR space exists in the memory-mapped bus.44 range of the DCSR space.57 This node represents the region of DCSR space allocated to the EPU98 offset and length of the DCSR space registers of the device114 This node represents the region of DCSR space allocated to the NPC127 offset and length of the DCSR space registers of the device129 The Nexus Port controller occupies two regions in the DCSR space151 This node represents the region of DCSR space allocated to the NXC[all …]
95 DCSR(prtd->dma_ch) = DCSR_RUN; in pxa2xx_pcm_trigger()101 DCSR(prtd->dma_ch) &= ~DCSR_RUN; in pxa2xx_pcm_trigger()105 DCSR(prtd->dma_ch) |= DCSR_RUN; in pxa2xx_pcm_trigger()109 DCSR(prtd->dma_ch) |= DCSR_RUN; in pxa2xx_pcm_trigger()146 DCSR(prtd->dma_ch) &= ~DCSR_RUN; in __pxa2xx_pcm_prepare()147 DCSR(prtd->dma_ch) = 0; in __pxa2xx_pcm_prepare()161 dcsr = DCSR(dma_ch); in pxa2xx_pcm_dma_irq()162 DCSR(dma_ch) = dcsr & ~DCSR_STOPIRQEN; in pxa2xx_pcm_dma_irq()
117 DCSR(pd->dma_channel) = 0; in pxa_qc_prep()149 DCSR(pd->dma_channel) = DCSR_RUN; in pxa_bmdma_start()159 if ((DCSR(pd->dma_channel) & DCSR_RUN) && in pxa_bmdma_stop()163 DCSR(pd->dma_channel) = 0; in pxa_bmdma_stop()225 pd->dma_dcsr = DCSR(dma); in pxa_ata_dma_irq()226 DCSR(dma) = pd->dma_dcsr; in pxa_ata_dma_irq()359 DCSR(data->dma_channel) = 0; in pxa_ata_probe()
153 DCSR(si->rxdma) = DCSR_NODESC; in pxa_irda_fir_dma_rx_start()157 DCSR(si->rxdma) |= DCSR_RUN; in pxa_irda_fir_dma_rx_start()162 DCSR(si->txdma) = DCSR_NODESC; in pxa_irda_fir_dma_tx_start()166 DCSR(si->txdma) |= DCSR_RUN; in pxa_irda_fir_dma_tx_start()205 DCSR(si->rxdma) &= ~DCSR_RUN; in pxa_irda_set_speed()347 int dcsr = DCSR(channel); in pxa_irda_fir_dma_rx_irq()349 DCSR(channel) = dcsr & ~DCSR_RUN; in pxa_irda_fir_dma_rx_irq()361 dcsr = DCSR(channel); in pxa_irda_fir_dma_tx_irq()362 DCSR(channel) = dcsr & ~DCSR_RUN; in pxa_irda_fir_dma_tx_irq()472 DCSR(si->rxdma) &= ~DCSR_RUN; in pxa_irda_fir_irq()[all …]
140 dcsr = DCSR(chan); in dbg_show_chan_state()306 DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; in pxa_request_dma()332 DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; in pxa_free_dma()355 DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; in dma_irq_handler()375 DCSR(i) = 0; in pxa_init_dma()
381 DCSR(dma) = DCSR_NODESC; in smc_pxa_dma_insl()386 DCSR(dma) = DCSR_NODESC | DCSR_RUN; in smc_pxa_dma_insl()387 while (!(DCSR(dma) & DCSR_STOPSTATE)) in smc_pxa_dma_insl()389 DCSR(dma) = 0; in smc_pxa_dma_insl()420 DCSR(dma) = DCSR_NODESC; in smc_pxa_dma_insw()425 DCSR(dma) = DCSR_NODESC | DCSR_RUN; in smc_pxa_dma_insw()426 while (!(DCSR(dma) & DCSR_STOPSTATE)) in smc_pxa_dma_insw()428 DCSR(dma) = 0; in smc_pxa_dma_insw()436 DCSR(dma) = 0; in smc_pxa_dma_irq()
229 if (DCSR(dma) & DCSR_BUSERR) { \232 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \262 DCSR(dma) = DCSR_NODESC; in smc_pxa_dma_insl()267 DCSR(dma) = DCSR_NODESC | DCSR_RUN; in smc_pxa_dma_insl()290 DCSR(dma) = DCSR_NODESC; in smc_pxa_dma_outsl()295 DCSR(dma) = DCSR_NODESC | DCSR_RUN; in smc_pxa_dma_outsl()
522 while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit) in wait_dma_channel_stop()533 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; in dma_error_stop()534 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; in dma_error_stop()558 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; in dma_transfer_complete()559 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; in dma_transfer_complete()598 u32 irq_status = DCSR(channel) & DMA_INT_MASK; in dma_handler()641 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { in dma_transfer()1102 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; in pump_transfers()1119 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; in pump_transfers()1142 DCSR(drv_data->rx_channel) |= DCSR_RUN; in pump_transfers()[all …]
6 #define DCSR(n) DMAC_REG((n) << 2) macro
62 #define DCSR(n) (n) macro
251 DCSR(host->dma) = DCSR_RUN; in pxamci_setup_data()343 DCSR(host->dma) = DCSR_RUN; in pxamci_cmd_done()358 DCSR(host->dma) = 0; in pxamci_data_done()555 int dcsr = DCSR(dma); in pxamci_dma_irq()556 DCSR(dma) = dcsr & ~DCSR_STOPIRQEN; in pxamci_dma_irq()
568 DCSR(pcdev->dma_chans[i]) = DCSR_RUN; in pxa_dma_start_channels()579 DCSR(pcdev->dma_chans[i]) = 0; in pxa_dma_stop_channels()752 status = DCSR(channel); in pxa_camera_dma_irq()753 DCSR(channel) = status; in pxa_camera_dma_irq()1006 DCSR(pcdev->dma_chans[0]) = 0; in pxa_camera_remove_device()1007 DCSR(pcdev->dma_chans[1]) = 0; in pxa_camera_remove_device()1008 DCSR(pcdev->dma_chans[2]) = 0; in pxa_camera_remove_device()
401 DCSR(info->data_dma_ch) |= DCSR_RUN; in start_data_dma()409 dcsr = DCSR(channel); in pxa3xx_nand_data_dma_irq()410 DCSR(channel) = dcsr; in pxa3xx_nand_data_dma_irq()