Searched refs:Control_1 (Results 1 – 2 of 2) sorted by relevance
104 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) && in RXD_IS_UP2DT()2510 if ((rxdp->Control_1 & RXD_OWN_XENA) && in fill_rx_buffers()2532 first_rxdp->Control_1 |= RXD_OWN_XENA; in fill_rx_buffers()2636 rxdp->Control_1 |= RXD_OWN_XENA; in fill_rx_buffers()2646 first_rxdp->Control_1 |= RXD_OWN_XENA; in fill_rx_buffers()2661 first_rxdp->Control_1 |= RXD_OWN_XENA; in fill_rx_buffers()3028 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) && in tx_intr_handler()3032 if (txdlp->Control_1 & TXD_T_CODE) { in tx_intr_handler()3034 err = txdlp->Control_1 & TXD_T_CODE; in tx_intr_handler()4128 txdp->Control_1 |= TXD_TCP_LSO_EN; in s2io_xmit()[all …]
493 u64 Control_1; member534 u64 Control_1; member