1 /*
2 * Driver for Digigram VX soundcards
3 *
4 * Hardware core part
5 *
6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #ifndef __SOUND_VX_COMMON_H
24 #define __SOUND_VX_COMMON_H
25
26 #include <sound/pcm.h>
27 #include <sound/hwdep.h>
28 #include <linux/interrupt.h>
29
30 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
31 #if !defined(CONFIG_USE_VXLOADER) && !defined(CONFIG_SND_VX_LIB) /* built-in kernel */
32 #define SND_VX_FW_LOADER /* use the standard firmware loader */
33 #endif
34 #endif
35
36 struct firmware;
37 struct device;
38
39 #define VX_DRIVER_VERSION 0x010000 /* 1.0.0 */
40
41 /*
42 */
43 #define SIZE_MAX_CMD 0x10
44 #define SIZE_MAX_STATUS 0x10
45
46 struct vx_rmh {
47 u16 LgCmd; /* length of the command to send (WORDs) */
48 u16 LgStat; /* length of the status received (WORDs) */
49 u32 Cmd[SIZE_MAX_CMD];
50 u32 Stat[SIZE_MAX_STATUS];
51 u16 DspStat; /* status type, RMP_SSIZE_XXX */
52 };
53
54 typedef u64 pcx_time_t;
55
56 #define VX_MAX_PIPES 16
57 #define VX_MAX_PERIODS 32
58 #define VX_MAX_CODECS 2
59
60 struct vx_ibl_info {
61 int size; /* the current IBL size (0 = query) in bytes */
62 int max_size; /* max. IBL size in bytes */
63 int min_size; /* min. IBL size in bytes */
64 int granularity; /* granularity */
65 };
66
67 struct vx_pipe {
68 int number;
69 unsigned int is_capture: 1;
70 unsigned int data_mode: 1;
71 unsigned int running: 1;
72 unsigned int prepared: 1;
73 int channels;
74 unsigned int differed_type;
75 pcx_time_t pcx_time;
76 struct snd_pcm_substream *substream;
77
78 int hbuf_size; /* H-buffer size in bytes */
79 int buffer_bytes; /* the ALSA pcm buffer size in bytes */
80 int period_bytes; /* the ALSA pcm period size in bytes */
81 int hw_ptr; /* the current hardware pointer in bytes */
82 int position; /* the current position in frames (playback only) */
83 int transferred; /* the transferred size (per period) in frames */
84 int align; /* size of alignment */
85 u64 cur_count; /* current sample position (for playback) */
86
87 unsigned int references; /* an output pipe may be used for monitoring and/or playback */
88 struct vx_pipe *monitoring_pipe; /* pointer to the monitoring pipe (capture pipe only)*/
89
90 struct tasklet_struct start_tq;
91 };
92
93 struct vx_core;
94
95 struct snd_vx_ops {
96 /* low-level i/o */
97 unsigned char (*in8)(struct vx_core *chip, int reg);
98 unsigned int (*in32)(struct vx_core *chip, int reg);
99 void (*out8)(struct vx_core *chip, int reg, unsigned char val);
100 void (*out32)(struct vx_core *chip, int reg, unsigned int val);
101 /* irq */
102 int (*test_and_ack)(struct vx_core *chip);
103 void (*validate_irq)(struct vx_core *chip, int enable);
104 /* codec */
105 void (*write_codec)(struct vx_core *chip, int codec, unsigned int data);
106 void (*akm_write)(struct vx_core *chip, int reg, unsigned int data);
107 void (*reset_codec)(struct vx_core *chip);
108 void (*change_audio_source)(struct vx_core *chip, int src);
109 void (*set_clock_source)(struct vx_core *chp, int src);
110 /* chip init */
111 int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw);
112 void (*reset_dsp)(struct vx_core *chip);
113 void (*reset_board)(struct vx_core *chip, int cold_reset);
114 int (*add_controls)(struct vx_core *chip);
115 /* pcm */
116 void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
117 struct vx_pipe *pipe, int count);
118 void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
119 struct vx_pipe *pipe, int count);
120 };
121
122 struct snd_vx_hardware {
123 const char *name;
124 int type; /* VX_TYPE_XXX */
125
126 /* hardware specs */
127 unsigned int num_codecs;
128 unsigned int num_ins;
129 unsigned int num_outs;
130 unsigned int output_level_max;
131 const unsigned int *output_level_db_scale;
132 };
133
134 /* hwdep id string */
135 #define SND_VX_HWDEP_ID "VX Loader"
136
137 /* hardware type */
138 enum {
139 /* VX222 PCI */
140 VX_TYPE_BOARD, /* old VX222 PCI */
141 VX_TYPE_V2, /* VX222 V2 PCI */
142 VX_TYPE_MIC, /* VX222 Mic PCI */
143 /* VX-pocket */
144 VX_TYPE_VXPOCKET, /* VXpocket V2 */
145 VX_TYPE_VXP440, /* VXpocket 440 */
146 VX_TYPE_NUMS
147 };
148
149 /* chip status */
150 enum {
151 VX_STAT_XILINX_LOADED = (1 << 0), /* devices are registered */
152 VX_STAT_DEVICE_INIT = (1 << 1), /* devices are registered */
153 VX_STAT_CHIP_INIT = (1 << 2), /* all operational */
154 VX_STAT_IN_SUSPEND = (1 << 10), /* in suspend phase */
155 VX_STAT_IS_STALE = (1 << 15) /* device is stale */
156 };
157
158 /* min/max values for analog output for old codecs */
159 #define VX_ANALOG_OUT_LEVEL_MAX 0xe3
160
161 struct vx_core {
162 /* ALSA stuff */
163 struct snd_card *card;
164 struct snd_pcm *pcm[VX_MAX_CODECS];
165 int type; /* VX_TYPE_XXX */
166
167 int irq;
168 /* ports are defined externally */
169
170 /* low-level functions */
171 struct snd_vx_hardware *hw;
172 struct snd_vx_ops *ops;
173
174 spinlock_t lock;
175 spinlock_t irq_lock;
176 struct tasklet_struct tq;
177
178 unsigned int chip_status;
179 unsigned int pcm_running;
180
181 struct device *dev;
182 struct snd_hwdep *hwdep;
183
184 struct vx_rmh irq_rmh; /* RMH used in interrupts */
185
186 unsigned int audio_info; /* see VX_AUDIO_INFO */
187 unsigned int audio_ins;
188 unsigned int audio_outs;
189 struct vx_pipe **playback_pipes;
190 struct vx_pipe **capture_pipes;
191
192 /* clock and audio sources */
193 unsigned int audio_source; /* current audio input source */
194 unsigned int audio_source_target;
195 unsigned int clock_mode; /* clock mode (VX_CLOCK_MODE_XXX) */
196 unsigned int clock_source; /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */
197 unsigned int freq; /* current frequency */
198 unsigned int freq_detected; /* detected frequency from digital in */
199 unsigned int uer_detected; /* VX_UER_MODE_XXX */
200 unsigned int uer_bits; /* IEC958 status bits */
201 struct vx_ibl_info ibl; /* IBL information */
202
203 /* mixer setting */
204 int output_level[VX_MAX_CODECS][2]; /* analog output level */
205 int audio_gain[2][4]; /* digital audio level (playback/capture) */
206 unsigned char audio_active[4]; /* mute/unmute on digital playback */
207 int audio_monitor[4]; /* playback hw-monitor level */
208 unsigned char audio_monitor_active[4]; /* playback hw-monitor mute/unmute */
209
210 struct mutex mixer_mutex;
211
212 const struct firmware *firmware[4]; /* loaded firmware data */
213 };
214
215
216 /*
217 * constructor
218 */
219 struct vx_core *snd_vx_create(struct snd_card *card, struct snd_vx_hardware *hw,
220 struct snd_vx_ops *ops, int extra_size);
221 int snd_vx_setup_firmware(struct vx_core *chip);
222 int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp);
223 int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp);
224 int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp);
225
226 void snd_vx_free_firmware(struct vx_core *chip);
227
228 /*
229 * interrupt handler; exported for pcmcia
230 */
231 irqreturn_t snd_vx_irq_handler(int irq, void *dev);
232
233 /*
234 * lowlevel functions
235 */
vx_test_and_ack(struct vx_core * chip)236 static inline int vx_test_and_ack(struct vx_core *chip)
237 {
238 return chip->ops->test_and_ack(chip);
239 }
240
vx_validate_irq(struct vx_core * chip,int enable)241 static inline void vx_validate_irq(struct vx_core *chip, int enable)
242 {
243 chip->ops->validate_irq(chip, enable);
244 }
245
snd_vx_inb(struct vx_core * chip,int reg)246 static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg)
247 {
248 return chip->ops->in8(chip, reg);
249 }
250
snd_vx_inl(struct vx_core * chip,int reg)251 static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg)
252 {
253 return chip->ops->in32(chip, reg);
254 }
255
snd_vx_outb(struct vx_core * chip,int reg,unsigned char val)256 static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val)
257 {
258 chip->ops->out8(chip, reg, val);
259 }
260
snd_vx_outl(struct vx_core * chip,int reg,unsigned int val)261 static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val)
262 {
263 chip->ops->out32(chip, reg, val);
264 }
265
266 #define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg)
267 #define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val)
268 #define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg)
269 #define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val)
270
vx_reset_dsp(struct vx_core * chip)271 static inline void vx_reset_dsp(struct vx_core *chip)
272 {
273 chip->ops->reset_dsp(chip);
274 }
275
276 int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh);
277 int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh);
278 int vx_send_rih(struct vx_core *chip, int cmd);
279 int vx_send_rih_nolock(struct vx_core *chip, int cmd);
280
281 void vx_reset_codec(struct vx_core *chip, int cold_reset);
282
283 /*
284 * check the bit on the specified register
285 * returns zero if a bit matches, or a negative error code.
286 * exported for vxpocket driver
287 */
288 int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time);
289 #define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time)
290 #define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200)
291 #define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL)
292
293
294 /*
295 * pseudo-DMA transfer
296 */
vx_pseudo_dma_write(struct vx_core * chip,struct snd_pcm_runtime * runtime,struct vx_pipe * pipe,int count)297 static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
298 struct vx_pipe *pipe, int count)
299 {
300 chip->ops->dma_write(chip, runtime, pipe, count);
301 }
302
vx_pseudo_dma_read(struct vx_core * chip,struct snd_pcm_runtime * runtime,struct vx_pipe * pipe,int count)303 static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
304 struct vx_pipe *pipe, int count)
305 {
306 chip->ops->dma_read(chip, runtime, pipe, count);
307 }
308
309
310
311 /* error with hardware code,
312 * the return value is -(VX_ERR_MASK | actual-hw-error-code)
313 */
314 #define VX_ERR_MASK 0x1000000
315 #define vx_get_error(err) (-(err) & ~VX_ERR_MASK)
316
317
318 /*
319 * pcm stuff
320 */
321 int snd_vx_pcm_new(struct vx_core *chip);
322 void vx_pcm_update_intr(struct vx_core *chip, unsigned int events);
323
324 /*
325 * mixer stuff
326 */
327 int snd_vx_mixer_new(struct vx_core *chip);
328 void vx_toggle_dac_mute(struct vx_core *chip, int mute);
329 int vx_sync_audio_source(struct vx_core *chip);
330 int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active);
331
332 /*
333 * IEC958 & clock stuff
334 */
335 void vx_set_iec958_status(struct vx_core *chip, unsigned int bits);
336 int vx_set_clock(struct vx_core *chip, unsigned int freq);
337 void vx_set_internal_clock(struct vx_core *chip, unsigned int freq);
338 int vx_change_frequency(struct vx_core *chip);
339
340
341 /*
342 * PM
343 */
344 int snd_vx_suspend(struct vx_core *card, pm_message_t state);
345 int snd_vx_resume(struct vx_core *card);
346
347 /*
348 * hardware constants
349 */
350
351 #define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD)
352 #define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET)
353
354 /* audio input source */
355 enum {
356 VX_AUDIO_SRC_DIGITAL,
357 VX_AUDIO_SRC_LINE,
358 VX_AUDIO_SRC_MIC
359 };
360
361 /* clock source */
362 enum {
363 INTERNAL_QUARTZ,
364 UER_SYNC
365 };
366
367 /* clock mode */
368 enum {
369 VX_CLOCK_MODE_AUTO, /* depending on the current audio source */
370 VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */
371 VX_CLOCK_MODE_EXTERNAL /* fixed to UER sync */
372 };
373
374 /* SPDIF/UER type */
375 enum {
376 VX_UER_MODE_CONSUMER,
377 VX_UER_MODE_PROFESSIONAL,
378 VX_UER_MODE_NOT_PRESENT,
379 };
380
381 /* register indices */
382 enum {
383 VX_ICR,
384 VX_CVR,
385 VX_ISR,
386 VX_IVR,
387 VX_RXH,
388 VX_TXH = VX_RXH,
389 VX_RXM,
390 VX_TXM = VX_RXM,
391 VX_RXL,
392 VX_TXL = VX_RXL,
393 VX_DMA,
394 VX_CDSP,
395 VX_RFREQ,
396 VX_RUER_V2,
397 VX_GAIN,
398 VX_DATA = VX_GAIN,
399 VX_MEMIRQ,
400 VX_ACQ,
401 VX_BIT0,
402 VX_BIT1,
403 VX_MIC0,
404 VX_MIC1,
405 VX_MIC2,
406 VX_MIC3,
407 VX_PLX0,
408 VX_PLX1,
409 VX_PLX2,
410
411 VX_LOFREQ, // V2: ACQ, VP: RFREQ
412 VX_HIFREQ, // V2: BIT0, VP: RUER_V2
413 VX_CSUER, // V2: BIT1, VP: BIT0
414 VX_RUER, // V2: RUER_V2, VP: BIT1
415
416 VX_REG_MAX,
417
418 /* aliases for VX board */
419 VX_RESET_DMA = VX_ISR,
420 VX_CFG = VX_RFREQ,
421 VX_STATUS = VX_MEMIRQ,
422 VX_SELMIC = VX_MIC0,
423 VX_COMPOT = VX_MIC1,
424 VX_SCOMPR = VX_MIC2,
425 VX_GLIMIT = VX_MIC3,
426 VX_INTCSR = VX_PLX0,
427 VX_CNTRL = VX_PLX1,
428 VX_GPIOC = VX_PLX2,
429
430 /* aliases for VXPOCKET board */
431 VX_MICRO = VX_MEMIRQ,
432 VX_CODEC2 = VX_MEMIRQ,
433 VX_DIALOG = VX_ACQ,
434
435 };
436
437 /* RMH status type */
438 enum {
439 RMH_SSIZE_FIXED = 0, /* status size given by the driver (in LgStat) */
440 RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */
441 RMH_SSIZE_MASK = 2, /* status size given in bitmask */
442 };
443
444
445 /* bits for ICR register */
446 #define ICR_HF1 0x10
447 #define ICR_HF0 0x08
448 #define ICR_TREQ 0x02 /* Interrupt mode + HREQ set on for transfer (->DSP) request */
449 #define ICR_RREQ 0x01 /* Interrupt mode + RREQ set on for transfer (->PC) request */
450
451 /* bits for CVR register */
452 #define CVR_HC 0x80
453
454 /* bits for ISR register */
455 #define ISR_HF3 0x10
456 #define ISR_HF2 0x08
457 #define ISR_CHK 0x10
458 #define ISR_ERR 0x08
459 #define ISR_TX_READY 0x04
460 #define ISR_TX_EMPTY 0x02
461 #define ISR_RX_FULL 0x01
462
463 /* Constants used to access the DATA register */
464 #define VX_DATA_CODEC_MASK 0x80
465 #define VX_DATA_XICOR_MASK 0x80
466
467 /* Constants used to access the CSUER register (both for VX2 and VXP) */
468 #define VX_SUER_FREQ_MASK 0x0c
469 #define VX_SUER_FREQ_32KHz_MASK 0x0c
470 #define VX_SUER_FREQ_44KHz_MASK 0x00
471 #define VX_SUER_FREQ_48KHz_MASK 0x04
472 #define VX_SUER_DATA_PRESENT_MASK 0x02
473 #define VX_SUER_CLOCK_PRESENT_MASK 0x01
474
475 #define VX_CUER_HH_BITC_SEL_MASK 0x08
476 #define VX_CUER_MH_BITC_SEL_MASK 0x04
477 #define VX_CUER_ML_BITC_SEL_MASK 0x02
478 #define VX_CUER_LL_BITC_SEL_MASK 0x01
479
480 #define XX_UER_CBITS_OFFSET_MASK 0x1f
481
482
483 /* bits for audio_info */
484 #define VX_AUDIO_INFO_REAL_TIME (1<<0) /* real-time processing available */
485 #define VX_AUDIO_INFO_OFFLINE (1<<1) /* offline processing available */
486 #define VX_AUDIO_INFO_MPEG1 (1<<5)
487 #define VX_AUDIO_INFO_MPEG2 (1<<6)
488 #define VX_AUDIO_INFO_LINEAR_8 (1<<7)
489 #define VX_AUDIO_INFO_LINEAR_16 (1<<8)
490 #define VX_AUDIO_INFO_LINEAR_24 (1<<9)
491
492 /* DSP Interrupt Request values */
493 #define VXP_IRQ_OFFSET 0x40 /* add 0x40 offset for vxpocket and vx222/v2 */
494 /* call with vx_send_irq_dsp() */
495 #define IRQ_MESS_WRITE_END 0x30
496 #define IRQ_MESS_WRITE_NEXT 0x32
497 #define IRQ_MESS_READ_NEXT 0x34
498 #define IRQ_MESS_READ_END 0x36
499 #define IRQ_MESSAGE 0x38
500 #define IRQ_RESET_CHK 0x3A
501 #define IRQ_CONNECT_STREAM_NEXT 0x26
502 #define IRQ_CONNECT_STREAM_END 0x28
503 #define IRQ_PAUSE_START_CONNECT 0x2A
504 #define IRQ_END_CONNECTION 0x2C
505
506 /* Is there async. events pending ( IT Source Test ) */
507 #define ASYNC_EVENTS_PENDING 0x008000
508 #define HBUFFER_EVENTS_PENDING 0x004000 // Not always accurate
509 #define NOTIF_EVENTS_PENDING 0x002000
510 #define TIME_CODE_EVENT_PENDING 0x001000
511 #define FREQUENCY_CHANGE_EVENT_PENDING 0x000800
512 #define END_OF_BUFFER_EVENTS_PENDING 0x000400
513 #define FATAL_DSP_ERROR 0xff0000
514
515 /* Stream Format Header Defines */
516 #define HEADER_FMT_BASE 0xFED00000
517 #define HEADER_FMT_MONO 0x000000C0
518 #define HEADER_FMT_INTEL 0x00008000
519 #define HEADER_FMT_16BITS 0x00002000
520 #define HEADER_FMT_24BITS 0x00004000
521 #define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.*/
522 #define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less then 32k.*/
523
524 /* Constants used to access the Codec */
525 #define XX_CODEC_SELECTOR 0x20
526 /* codec commands */
527 #define XX_CODEC_ADC_CONTROL_REGISTER 0x01
528 #define XX_CODEC_DAC_CONTROL_REGISTER 0x02
529 #define XX_CODEC_LEVEL_LEFT_REGISTER 0x03
530 #define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04
531 #define XX_CODEC_PORT_MODE_REGISTER 0x05
532 #define XX_CODEC_STATUS_REPORT_REGISTER 0x06
533 #define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07
534
535 /*
536 * Audio-level control values
537 */
538 #define CVAL_M110DB 0x000 /* -110dB */
539 #define CVAL_M99DB 0x02C
540 #define CVAL_M21DB 0x163
541 #define CVAL_M18DB 0x16F
542 #define CVAL_M10DB 0x18F
543 #define CVAL_0DB 0x1B7
544 #define CVAL_18DB 0x1FF /* +18dB */
545 #define CVAL_MAX 0x1FF
546
547 #define AUDIO_IO_HAS_MUTE_LEVEL 0x400000
548 #define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000
549 #define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000
550 #define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01
551 #define VALID_AUDIO_IO_MONITORING_LEVEL 0x02
552 #define VALID_AUDIO_IO_MUTE_LEVEL 0x04
553 #define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08
554 #define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10
555
556
557 #endif /* __SOUND_VX_COMMON_H */
558