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Searched refs:CCR1 (Results 1 – 4 of 4) sorted by relevance

/linux-3.4.99/drivers/net/wan/
Ddscc4.c270 #define CCR1 0x0c macro
869 scc_writel(0x02408000, dpriv, dev, CCR1); in dscc4_init_registers()
1425 state = scc_readl(dpriv, CCR1); in dscc4_loopback_setting()
1433 scc_writel(state, dpriv, dev, CCR1); in dscc4_loopback_setting()
1450 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1); in dscc4_crc_setting()
Dpc300-falc-lh.h1133 #define CCR1 0x09 /* Common Configuration Reg 1 */ macro
Dpc300_drv.c921 cpc_writeb(falcbase + F_REG(CCR1, ch), 0); in falc_init_t1()
1133 cpc_writeb(falcbase + F_REG(CCR1, ch), 0); in falc_init_e1()
/linux-3.4.99/drivers/char/pcmcia/
Dsynclink_cs.c270 #define CCR1 0x2d macro
2959 write_reg(info, CHB + CCR1, 0x17); in enable_auxclk()
3005 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0); in loopback_enable()
3006 write_reg(info, CHA + CCR1, val); in loopback_enable()
3119 write_reg(info, CHA + CCR1, val); in hdlc_mode()
3446 write_reg(info, CHA + CCR1, 0x1f); in async_mode()
3569 set_reg_bits(info, CHA + CCR1, BIT3); in tx_set_idle()
3571 clear_reg_bits(info, CHA + CCR1, BIT3); in tx_set_idle()