Searched refs:C400_CONTROL_STATUS_REG (Results 1 – 3 of 3) sorted by relevance
581 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE | CSR_TRANS_DIR); in NCR5380_pread()587 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { in NCR5380_pread()591 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY); in NCR5380_pread()608 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()627 if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) in NCR5380_pread()635 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG) in NCR5380_pread()666 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE); in NCR5380_pwrite()669 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { in NCR5380_pwrite()677 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pwrite()692 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pwrite()[all …]
170 #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */ macro
889 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE); in NCR5380_init()