1 /* 2 * Freescale CLKCTRL Register Definitions 3 * 4 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 5 * Copyright 2008-2010 Freescale Semiconductor, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * 21 * This file is created by xml file. Don't Edit it. 22 * 23 * Xml Revision: 1.48 24 * Template revision: 26195 25 */ 26 27 #ifndef __REGS_CLKCTRL_MX23_H__ 28 #define __REGS_CLKCTRL_MX23_H__ 29 30 31 #define HW_CLKCTRL_PLLCTRL0 (0x00000000) 32 #define HW_CLKCTRL_PLLCTRL0_SET (0x00000004) 33 #define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008) 34 #define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c) 35 36 #define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 37 #define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 38 #define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ 39 (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL) 40 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 41 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 42 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 43 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 44 #define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 45 #define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 46 #define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ 47 (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL) 48 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 49 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 50 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 51 #define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 52 #define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 53 #define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 54 #define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ 55 (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL) 56 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 57 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 58 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 59 #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 60 #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 61 #define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 62 63 #define HW_CLKCTRL_PLLCTRL1 (0x00000010) 64 65 #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 66 #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 67 #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 68 #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF 69 #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ 70 (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT) 71 72 #define HW_CLKCTRL_CPU (0x00000020) 73 #define HW_CLKCTRL_CPU_SET (0x00000024) 74 #define HW_CLKCTRL_CPU_CLR (0x00000028) 75 #define HW_CLKCTRL_CPU_TOG (0x0000002c) 76 77 #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 78 #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 79 #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 80 #define BP_CLKCTRL_CPU_DIV_XTAL 16 81 #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 82 #define BF_CLKCTRL_CPU_DIV_XTAL(v) \ 83 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) 84 #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 85 #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 86 #define BP_CLKCTRL_CPU_DIV_CPU 0 87 #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F 88 #define BF_CLKCTRL_CPU_DIV_CPU(v) \ 89 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) 90 91 #define HW_CLKCTRL_HBUS (0x00000030) 92 #define HW_CLKCTRL_HBUS_SET (0x00000034) 93 #define HW_CLKCTRL_HBUS_CLR (0x00000038) 94 #define HW_CLKCTRL_HBUS_TOG (0x0000003c) 95 96 #define BM_CLKCTRL_HBUS_BUSY 0x20000000 97 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 98 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 99 #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 100 #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 101 #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 102 #define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 103 #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 104 #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 105 #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 106 #define BP_CLKCTRL_HBUS_SLOW_DIV 16 107 #define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 108 #define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ 109 (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) 110 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 111 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 112 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 113 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 114 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 115 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 116 #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 117 #define BP_CLKCTRL_HBUS_DIV 0 118 #define BM_CLKCTRL_HBUS_DIV 0x0000001F 119 #define BF_CLKCTRL_HBUS_DIV(v) \ 120 (((v) << 0) & BM_CLKCTRL_HBUS_DIV) 121 122 #define HW_CLKCTRL_XBUS (0x00000040) 123 124 #define BM_CLKCTRL_XBUS_BUSY 0x80000000 125 #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 126 #define BP_CLKCTRL_XBUS_DIV 0 127 #define BM_CLKCTRL_XBUS_DIV 0x000003FF 128 #define BF_CLKCTRL_XBUS_DIV(v) \ 129 (((v) << 0) & BM_CLKCTRL_XBUS_DIV) 130 131 #define HW_CLKCTRL_XTAL (0x00000050) 132 #define HW_CLKCTRL_XTAL_SET (0x00000054) 133 #define HW_CLKCTRL_XTAL_CLR (0x00000058) 134 #define HW_CLKCTRL_XTAL_TOG (0x0000005c) 135 136 #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 137 #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 138 #define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 139 #define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 140 #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 141 #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 142 #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 143 #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 144 #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 145 #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 146 #define BP_CLKCTRL_XTAL_DIV_UART 0 147 #define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 148 #define BF_CLKCTRL_XTAL_DIV_UART(v) \ 149 (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) 150 151 #define HW_CLKCTRL_PIX (0x00000060) 152 153 #define BP_CLKCTRL_PIX_CLKGATE 31 154 #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 155 #define BM_CLKCTRL_PIX_BUSY 0x20000000 156 #define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 157 #define BP_CLKCTRL_PIX_DIV 0 158 #define BM_CLKCTRL_PIX_DIV 0x00000FFF 159 #define BF_CLKCTRL_PIX_DIV(v) \ 160 (((v) << 0) & BM_CLKCTRL_PIX_DIV) 161 162 #define HW_CLKCTRL_SSP (0x00000070) 163 164 #define BP_CLKCTRL_SSP_CLKGATE 31 165 #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 166 #define BM_CLKCTRL_SSP_BUSY 0x20000000 167 #define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 168 #define BP_CLKCTRL_SSP_DIV 0 169 #define BM_CLKCTRL_SSP_DIV 0x000001FF 170 #define BF_CLKCTRL_SSP_DIV(v) \ 171 (((v) << 0) & BM_CLKCTRL_SSP_DIV) 172 173 #define HW_CLKCTRL_GPMI (0x00000080) 174 175 #define BP_CLKCTRL_GPMI_CLKGATE 31 176 #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 177 #define BM_CLKCTRL_GPMI_BUSY 0x20000000 178 #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 179 #define BP_CLKCTRL_GPMI_DIV 0 180 #define BM_CLKCTRL_GPMI_DIV 0x000003FF 181 #define BF_CLKCTRL_GPMI_DIV(v) \ 182 (((v) << 0) & BM_CLKCTRL_GPMI_DIV) 183 184 #define HW_CLKCTRL_SPDIF (0x00000090) 185 186 #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 187 188 #define HW_CLKCTRL_EMI (0x000000a0) 189 190 #define BP_CLKCTRL_EMI_CLKGATE 31 191 #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 192 #define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 193 #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 194 #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 195 #define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 196 #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 197 #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 198 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 199 #define BP_CLKCTRL_EMI_DIV_XTAL 8 200 #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 201 #define BF_CLKCTRL_EMI_DIV_XTAL(v) \ 202 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) 203 #define BP_CLKCTRL_EMI_DIV_EMI 0 204 #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F 205 #define BF_CLKCTRL_EMI_DIV_EMI(v) \ 206 (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) 207 208 #define HW_CLKCTRL_IR (0x000000b0) 209 210 #define BM_CLKCTRL_IR_CLKGATE 0x80000000 211 #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 212 #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 213 #define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 214 #define BP_CLKCTRL_IR_IROV_DIV 16 215 #define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 216 #define BF_CLKCTRL_IR_IROV_DIV(v) \ 217 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) 218 #define BP_CLKCTRL_IR_IR_DIV 0 219 #define BM_CLKCTRL_IR_IR_DIV 0x000003FF 220 #define BF_CLKCTRL_IR_IR_DIV(v) \ 221 (((v) << 0) & BM_CLKCTRL_IR_IR_DIV) 222 223 #define HW_CLKCTRL_SAIF (0x000000c0) 224 225 #define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 226 #define BM_CLKCTRL_SAIF_BUSY 0x20000000 227 #define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 228 #define BP_CLKCTRL_SAIF_DIV 0 229 #define BM_CLKCTRL_SAIF_DIV 0x0000FFFF 230 #define BF_CLKCTRL_SAIF_DIV(v) \ 231 (((v) << 0) & BM_CLKCTRL_SAIF_DIV) 232 233 #define HW_CLKCTRL_TV (0x000000d0) 234 235 #define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 236 #define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 237 238 #define HW_CLKCTRL_ETM (0x000000e0) 239 240 #define BM_CLKCTRL_ETM_CLKGATE 0x80000000 241 #define BM_CLKCTRL_ETM_BUSY 0x20000000 242 #define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 243 #define BP_CLKCTRL_ETM_DIV 0 244 #define BM_CLKCTRL_ETM_DIV 0x0000003F 245 #define BF_CLKCTRL_ETM_DIV(v) \ 246 (((v) << 0) & BM_CLKCTRL_ETM_DIV) 247 248 #define HW_CLKCTRL_FRAC (0x000000f0) 249 #define HW_CLKCTRL_FRAC_SET (0x000000f4) 250 #define HW_CLKCTRL_FRAC_CLR (0x000000f8) 251 #define HW_CLKCTRL_FRAC_TOG (0x000000fc) 252 253 #define BP_CLKCTRL_FRAC_CLKGATEIO 31 254 #define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 255 #define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 256 #define BP_CLKCTRL_FRAC_IOFRAC 24 257 #define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000 258 #define BF_CLKCTRL_FRAC_IOFRAC(v) \ 259 (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC) 260 #define BP_CLKCTRL_FRAC_CLKGATEPIX 23 261 #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 262 #define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000 263 #define BP_CLKCTRL_FRAC_PIXFRAC 16 264 #define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 265 #define BF_CLKCTRL_FRAC_PIXFRAC(v) \ 266 (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC) 267 #define BP_CLKCTRL_FRAC_CLKGATEEMI 15 268 #define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 269 #define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000 270 #define BP_CLKCTRL_FRAC_EMIFRAC 8 271 #define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 272 #define BF_CLKCTRL_FRAC_EMIFRAC(v) \ 273 (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC) 274 #define BP_CLKCTRL_FRAC_CLKGATECPU 7 275 #define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080 276 #define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040 277 #define BP_CLKCTRL_FRAC_CPUFRAC 0 278 #define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F 279 #define BF_CLKCTRL_FRAC_CPUFRAC(v) \ 280 (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC) 281 282 #define HW_CLKCTRL_FRAC1 (0x00000100) 283 #define HW_CLKCTRL_FRAC1_SET (0x00000104) 284 #define HW_CLKCTRL_FRAC1_CLR (0x00000108) 285 #define HW_CLKCTRL_FRAC1_TOG (0x0000010c) 286 287 #define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 288 #define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 289 290 #define HW_CLKCTRL_CLKSEQ (0x00000110) 291 #define HW_CLKCTRL_CLKSEQ_SET (0x00000114) 292 #define HW_CLKCTRL_CLKSEQ_CLR (0x00000118) 293 #define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c) 294 295 #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 296 #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 297 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 298 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 299 #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 300 #define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 301 #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 302 #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 303 304 #define HW_CLKCTRL_RESET (0x00000120) 305 306 #define BM_CLKCTRL_RESET_CHIP 0x00000002 307 #define BM_CLKCTRL_RESET_DIG 0x00000001 308 309 #define HW_CLKCTRL_STATUS (0x00000130) 310 311 #define BP_CLKCTRL_STATUS_CPU_LIMIT 30 312 #define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 313 #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ 314 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) 315 316 #define HW_CLKCTRL_VERSION (0x00000140) 317 318 #define BP_CLKCTRL_VERSION_MAJOR 24 319 #define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 320 #define BF_CLKCTRL_VERSION_MAJOR(v) \ 321 (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) 322 #define BP_CLKCTRL_VERSION_MINOR 16 323 #define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 324 #define BF_CLKCTRL_VERSION_MINOR(v) \ 325 (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) 326 #define BP_CLKCTRL_VERSION_STEP 0 327 #define BM_CLKCTRL_VERSION_STEP 0x0000FFFF 328 #define BF_CLKCTRL_VERSION_STEP(v) \ 329 (((v) << 0) & BM_CLKCTRL_VERSION_STEP) 330 331 #endif /* __REGS_CLKCTRL_MX23_H__ */ 332