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Searched refs:BIT5 (Results 1 – 25 of 29) sorted by relevance

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/linux-3.4.99/drivers/scsi/
Dtmscsim.h186 #define BIT5 0x00000020 macro
211 #define SRB_COMMAND BIT5
228 #define SRB_ERROR BIT5
241 #define RESIDUAL_VALID BIT5
283 #define EN_ATN_STOP BIT5
345 #define LUN_CHECK BIT5
391 #define PARITY_ERR BIT5
400 #define DISCONNECTED BIT5
434 #define EN_GRP2_CMD BIT5
443 #define REDUCED_POWER BIT5
[all …]
Ddc395x.h70 #define BIT5 0x00000020 macro
133 #define SRB_ERROR BIT5
138 #define RESIDUAL_VALID BIT5
178 #define EN_TAG_QUEUEING BIT5
634 #define LUN_CHECK BIT5
/linux-3.4.99/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h114 #define EPROM_CMD_RESERVED_MASK BIT5
144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
159 #define RCR_ACRC32 BIT5
196 #define CAM_USEDK BIT5
220 #define SCR_NoSKMC BIT5
237 #define IMR_HCCADOK BIT5
250 #define TPPoll_CQ BIT5
290 #define AcmHw_ViqStatus BIT5
380 #define RRSR_9M BIT5
/linux-3.4.99/drivers/staging/vt6655/
D80211hdr.h43 #define BIT5 0x00000020 macro
166 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n) >> 8) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
187 #define WLAN_GET_CAP_INFO_SHORTPREAMBLE(n) ((((n) >> 8) & BIT5) >> 5)
201 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
223 #define WLAN_GET_CAP_INFO_SHORTPREAMBLE(n) (((n) & BIT5) >> 5)
Dhostap.h41 #define WLAN_RATE_9M BIT5
Dbssdb.h64 #define WLAN_STA_AUTHORIZED BIT5
/linux-3.4.99/drivers/staging/vt6656/
D80211hdr.h41 #define BIT5 0x00000020 macro
163 & (BIT4|BIT5|BIT6|BIT7)) >> 4)
184 #define WLAN_GET_CAP_INFO_SHORTPREAMBLE(n) ((((n) >> 8) & BIT5) >> 5)
197 #define WLAN_GET_FC_FSTYPE(n) ((((WORD)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
217 #define WLAN_GET_CAP_INFO_SHORTPREAMBLE(n) (((n) & BIT5) >> 5)
Dhostap.h41 #define WLAN_RATE_9M BIT5
Dbssdb.h65 #define WLAN_STA_AUTHORIZED BIT5
/linux-3.4.99/drivers/staging/rtl8192u/
Dr8192U_hw.h156 #define RCR_ACRC32 BIT5 // Accept CRC32 error packet
188 #define SCR_NoSKMC BIT5 //No Key Search for Multicast
234 #define AcmHw_ViqStatus BIT5
312 #define RRSR_9M BIT5
Dr8192U.h56 #define BIT5 0x00000020 macro
103 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
/linux-3.4.99/drivers/video/via/
Ddvi.c76 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
80 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); in viafb_tmds_trasmitter_identify()
410 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
422 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
Dhw.c1711 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); in device_screen_off()
1717 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); in device_screen_on()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1732 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1735 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1740 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1743 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2080 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); in viafb_set_dpa_gfx()
Dshare.h33 #define BIT5 0x20 macro
/linux-3.4.99/drivers/staging/keucr/
Dsmilecc.c43 #define BIT5 0x20 macro
/linux-3.4.99/drivers/tty/
Dsynclinkmp.c438 #define PE BIT5
439 #define ABT BIT5
2606 if (timerstatus0 & (BIT5 | BIT4)) in synclinkmp_interrupt()
2610 if (timerstatus1 & (BIT5 | BIT4)) in synclinkmp_interrupt()
4411 case 6: RegValue |= BIT5 + BIT3; break; in async_mode()
4412 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; in async_mode()
4574 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break; in hdlc_mode()
4575 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ in hdlc_mode()
4606 RegValue |= BIT6 + BIT5; in hdlc_mode()
4619 RegValue |= BIT6 + BIT5; in hdlc_mode()
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Dsynclink_gt.c423 #define IRQ_DCD BIT5
2239 if (status & (BIT5 + BIT4)) { in isr_rdma()
2264 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4162 case 7: val |= BIT5; break; in async_mode()
4163 case 8: val |= BIT5 + BIT4; break; in async_mode()
4202 case 7: val |= BIT5; break; in async_mode()
4203 case 8: val |= BIT5 + BIT4; break; in async_mode()
4326 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; in sync_mode()
4328 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4414 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
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Dsynclink.c492 #define RECEIVE_STATUS BIT5
508 #define RXSTATUS_BREAK_RECEIVED BIT5
509 #define RXSTATUS_ABORT_RECEIVED BIT5
548 #define TXSTATUS_ABORT_SENT BIT5
569 #define MISCSTATUS_CTS_LATCHED BIT5
594 #define SICR_CTS_ACTIVE BIT5
596 #define SICR_CTS (BIT5+BIT4)
629 #define TXSTATUS_ABORT_SENT BIT5
5919 RegValue |= BIT5; in usc_set_async_mode()
5976 RegValue |= BIT5; in usc_set_async_mode()
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/linux-3.4.99/include/linux/
Dsynclink.h23 #define BIT5 0x0020 macro
/linux-3.4.99/drivers/staging/rtl8187se/
Dr8180_rtl8225z2.c903 write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6)))); in SetZebraRFPowerState8185()
964 (u1bTmp | BIT5 | BIT6)); in SetZebraRFPowerState8185()
1024 write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6)); in SetZebraRFPowerState8185()
Dr8180_hw.h29 #define BIT5 0x00000020 macro
Dr8185b_init.c677 write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6)))); in ZEBRA_Config_85BASIC_HardCode()
1592 write_nic_byte(dev, 0x24e, (BIT5|BIT6|BIT0)); in rtl8185b_adapter_start()
/linux-3.4.99/drivers/char/pcmcia/
Dsynclink_cs.c672 #define CMD_RXFIFO_READ BIT5
901 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5)) in rx_ready_async()
3009 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5); in loopback_enable()
3136 val |= BIT5; in hdlc_mode()
3161 val |= BIT5; in hdlc_mode()
3224 val |= BIT5; in hdlc_mode()
3498 val |= BIT5; in async_mode()
3541 val |= BIT5; in async_mode()
3666 else if (!(status & BIT5)) { in rx_get_frame()
3697 if (status & BIT5) in rx_get_frame()
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/linux-3.4.99/drivers/staging/rtl8192e/
Drtl819x_Qos.h29 #define BIT5 0x00000020 macro
/linux-3.4.99/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h9 #define BIT5 0x00000020 macro

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