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Searched refs:BIT31 (Results 1 – 20 of 20) sorted by relevance

/linux-3.4.99/drivers/staging/rtl8192e/rtl8192e/
Drtl_cam.c36 ulcommand |= BIT31|BIT30; in CamResetAllEntry()
43 write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff)); in write_cam()
140 TargetCommand |= BIT31|BIT16; in setKey()
177 target_command = target_command | BIT31; in CAM_read_entry()
181 if (ulStatus & BIT31) in CAM_read_entry()
Dr8192E_hw.h146 #define RCR_ONLYERLPKT BIT31
191 #define CAM_CM_SecCAMPolling BIT31
210 #define CAM_POLLINIG BIT31
Drtl_debug.c638 target_command = target_command | BIT31; in proc_get_cam_register_1()
642 if (ulStatus & BIT31) in proc_get_cam_register_1()
679 target_command = target_command | BIT31; in proc_get_cam_register_2()
683 if (ulStatus & BIT31) in proc_get_cam_register_2()
720 target_command = target_command | BIT31; in proc_get_cam_register_3()
724 if (ulStatus & BIT31) in proc_get_cam_register_3()
Drtl_dm.c287 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); in dm_check_rate_adaptive()
290 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); in dm_check_rate_adaptive()
294 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); in dm_check_rate_adaptive()
297 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); in dm_check_rate_adaptive()
300 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); in dm_check_rate_adaptive()
Drtl_wx.c315 rt_global_debug_component &= BIT31; in r8192_wx_set_debugflag()
/linux-3.4.99/include/linux/
Dsynclink.h49 #define BIT31 0x80000000 macro
/linux-3.4.99/drivers/staging/rtl8192u/
Dr8192U_dm.c391 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; in dm_check_rate_adaptive()
394 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; in dm_check_rate_adaptive()
399 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; in dm_check_rate_adaptive()
404 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; in dm_check_rate_adaptive()
408 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; in dm_check_rate_adaptive()
Dr8192U_hw.h143 #define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size.
Dr8192U.h82 #define BIT31 0x80000000 macro
134 #define COMP_ERR BIT31 //for error out, always on
Dr8192U_core.c263 ulcommand |= BIT31|BIT30; in CamResetAllEntry()
272 write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff) ); in write_cam()
4033 target_command= target_command | BIT31; in CAM_read_entry()
4040 if(ulStatus & BIT31){ in CAM_read_entry()
6009 TargetCommand |= BIT31|BIT16; in setKey()
/linux-3.4.99/drivers/scsi/
Ddc395x.h44 #define BIT31 0x80000000 macro
Dtmscsim.h160 #define BIT31 0x80000000 macro
/linux-3.4.99/drivers/staging/rtl8187se/
Dr8180_hw.h47 #define BIT31 0x80000000 macro
/linux-3.4.99/drivers/staging/vt6655/
D80211hdr.h69 #define BIT31 0x80000000 macro
/linux-3.4.99/drivers/staging/vt6656/
D80211hdr.h67 #define BIT31 0x80000000 macro
/linux-3.4.99/drivers/staging/rtl8192e/
Drtl819x_Qos.h55 #define BIT31 0x80000000 macro
Drtllib.h150 #define RT_RF_LPS_LEVEL_ASPM BIT31
1883 #define RF_CHANGE_BY_SW BIT31
/linux-3.4.99/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h35 #define BIT31 0x80000000 macro
Dieee80211.h1764 #define RF_CHANGE_BY_SW BIT31
/linux-3.4.99/drivers/scsi/lpfc/
Dlpfc_hw4.h694 #define LPFC_SLI4_INTR31 BIT31