Searched refs:BIT12 (Results 1 – 15 of 15) sorted by relevance
144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \158 #define RCR_AICV BIT12230 #define IMR_RXFOVW BIT12257 #define TPPoll_StopVO BIT12387 #define RRSR_MCS0 BIT12
50 #define BIT12 0x00001000 macro171 #define WLAN_GET_FC_PWRMGT(n) ((((unsigned short)(n) << 8) & (BIT12)) >> 12)206 #define WLAN_GET_FC_PWRMGT(n) ((((unsigned short)(n)) & (BIT12)) >> 12)
48 #define BIT12 0x00001000 macro168 #define WLAN_GET_FC_PWRMGT(n) ((((WORD)(n) << 8) & (BIT12)) >> 12)202 #define WLAN_GET_FC_PWRMGT(n) ((((WORD)(n)) & (BIT12)) >> 12)
155 #define RCR_AICV BIT12 // Accept ICV error packet319 #define RRSR_MCS0 BIT12
63 #define BIT12 0x00001000 macro110 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
179 #define BIT12 0x00001000 macro218 #define SRB_ABORT_SENT BIT12
63 #define BIT12 0x00001000 macro
30 #define BIT12 0x1000 macro
562 #define MISCSTATUS_TXC BIT12583 #define SICR_TXC_INACTIVE BIT12584 #define SICR_TXC (BIT13+BIT12)1852 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12)); in shutdown()4688 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12)); in usc_set_sdlc_mode()4722 RegValue |= BIT12; in usc_set_sdlc_mode()4764 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()4839 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()5170 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break; in usc_set_sdlc_mode()6045 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); in usc_set_async_mode()[all …]
415 #define IRQ_TXIDLE BIT124309 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; in sync_mode()4310 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4311 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()4312 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4382 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; in sync_mode()4383 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4384 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()4385 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
36 #define BIT12 0x00001000 macro
16 #define BIT12 0x00001000 macro
395 #define RRSR_MCS0 BIT12
675 #define LPFC_SLI4_INTR12 BIT12
294 #define IRQ_UNDERRUN BIT12 // transmit data underrun