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Searched refs:BIT1 (Results 1 – 25 of 37) sorted by relevance

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/linux-3.4.99/drivers/scsi/
Dtmscsim.h190 #define BIT1 0x00000002 macro
195 #define UNIT_INFO_CHANGED BIT1
201 #define SCSI_SUPPORT BIT1
207 #define SRB_READY BIT1
224 #define ABORTION BIT1
232 #define RESET_DETECT BIT1
244 #define ABORT_DEV BIT1
279 #define SYNC_NEGO_DONE BIT1
334 #define SYNC_NEGO_ BIT1
341 #define GREATER_1G BIT1
[all …]
Ddc395x.h74 #define BIT1 0x00000002 macro
79 #define UNIT_INFO_CHANGED BIT1
85 #define SCSI_SUPPORT BIT1
121 #define RESET_DETECT BIT1
129 #define ABORTION BIT1
141 #define ABORT_DEV BIT1
174 #define SYNC_NEGO_DONE BIT1
630 #define GREATER_1G BIT1
/linux-3.4.99/drivers/staging/vt6655/
D80211hdr.h39 #define BIT1 0x00000002 macro
164 #define WLAN_GET_FC_PRVER(n) ((((unsigned short)(n) >> 8) & (BIT0 | BIT1))
177 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3))
178 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n) >> 8) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
183 #define WLAN_GET_CAP_INFO_IBSS(n) ((((n) >> 8) & BIT1) >> 1)
199 #define WLAN_GET_FC_PRVER(n) (((unsigned short)(n)) & (BIT0 | BIT1))
213 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n)) & (BIT0|BIT1|BIT2|BIT3))
214 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
219 #define WLAN_GET_CAP_INFO_IBSS(n) (((n) & BIT1) >> 1)
267 #define WLAN_GET_ERP_USE_PROTECTION(n) (((n) & BIT1) >> 1)
Dhostap.h37 #define WLAN_RATE_2M BIT1
Dbssdb.h56 #define WLAN_STA_ASSOC BIT1
Dioctl.c531 } else if (sStartAPCmd.byBasicRate & BIT1) { in private_ioctl()
534 } else if (sStartAPCmd.byBasicRate & BIT1) { in private_ioctl()
/linux-3.4.99/drivers/staging/vt6656/
D80211hdr.h37 #define BIT1 0x00000002 macro
160 #define WLAN_GET_FC_PRVER(n) ((((WORD)(n) >> 8) & (BIT0 | BIT1))
174 #define WLAN_GET_SEQ_FRGNUM(n) (((WORD)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3))
176 & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
180 #define WLAN_GET_CAP_INFO_IBSS(n) ((((n) >> 8) & BIT1) >> 1)
195 #define WLAN_GET_FC_PRVER(n) (((WORD)(n)) & (BIT0 | BIT1))
208 #define WLAN_GET_SEQ_FRGNUM(n) (((WORD)(n)) & (BIT0|BIT1|BIT2|BIT3))
209 #define WLAN_GET_SEQ_SEQNUM(n) ((((WORD)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
213 #define WLAN_GET_CAP_INFO_IBSS(n) (((n) & BIT1) >> 1)
258 #define WLAN_GET_ERP_USE_PROTECTION(n) (((n) & BIT1) >> 1)
Dhostap.h37 #define WLAN_RATE_2M BIT1
Dbssdb.h57 #define WLAN_STA_ASSOC BIT1
Dioctl.c518 } else if (sStartAPCmd.byBasicRate & BIT1) { in private_ioctl()
521 } else if (sStartAPCmd.byBasicRate & BIT1) { in private_ioctl()
/linux-3.4.99/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
162 #define RCR_APM BIT1
216 #define SCR_RxUseDK BIT1
241 #define IMR_VODOK BIT1
246 #define TPPoll_BEQ BIT1
286 #define AcmHw_BeqEn BIT1
294 #define AcmFw_ViqStatus BIT1
347 #define BW_OPMODE_5G BIT1
376 #define RRSR_2M BIT1
/linux-3.4.99/drivers/video/via/
Ddvi.c59 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
339 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
349 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
352 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
359 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
360 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
377 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
384 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
391 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
Dlcd.c359 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
534 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
577 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
622 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
666 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
668 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
688 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); in integrated_lvds_enable()
760 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
Dvia_utility.c184 viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1); in viafb_set_gamma_table()
Dshare.h29 #define BIT1 0x02 macro
/linux-3.4.99/drivers/staging/rtl8192u/
Dr8192U_hw.h159 #define RCR_APM BIT1 // Accept physical match packet
184 #define SCR_RxUseDK BIT1 //Force Rx Use Default Key
230 #define AcmHw_BeqEn BIT1
285 #define BW_OPMODE_5G BIT1
308 #define RRSR_2M BIT1
/linux-3.4.99/drivers/staging/rtl8187se/
Dr8180_hw.h25 #define BIT1 0x00000002 macro
181 #define RF_SW_CFG_SI BIT1
574 #define PWR_METER_EN BIT1
/linux-3.4.99/drivers/staging/rtl8192e/
Drtl819x_Qos.h25 #define BIT1 0x00000002 macro
276 #define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1)
277 #define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1)
/linux-3.4.99/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h5 #define BIT1 0x00000002 macro
398 #define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1)
399 #define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1)
/linux-3.4.99/drivers/tty/
Dsynclink_gt.c221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
383 #define MASK_PARITY BIT1
1884 if ((status = *(p+1) & (BIT1 + BIT0))) { in rx_async()
1885 if (status & BIT1) in rx_async()
1892 if (status & BIT1) in rx_async()
2074 if (status & BIT1) { in dcd_change()
3897 wr_reg32(info, RDCSR, BIT1); in rdma_reset()
3910 wr_reg32(info, TDCSR, BIT1); in tdma_reset()
3974 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_stop()
3999 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_start()
[all …]
Dsynclink.c496 #define IO_PIN BIT1
515 #define RXSTATUS_OVERRUN BIT1
553 #define TXSTATUS_UNDERRUN BIT1
573 #define MISCSTATUS_BRG1_ZERO BIT1
599 #define SICR_BRG1_ZERO BIT1
633 #define TXSTATUS_UNDERRUN BIT1
638 #define DICR_RECEIVE BIT1
1603 usc_OutDmaReg( info, CDIR, BIT9+BIT1 ); in mgsl_isr_receive_dma()
5241 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5304 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
[all …]
Dsynclinkmp.c418 #define TXRDYE BIT1
428 #define BRKD BIT1
429 #define ABTD BIT1
430 #define GAPD BIT1
2589 if (status & BIT1 << shift) in synclinkmp_interrupt()
2598 if (dmastatus & BIT1 << shift) in synclinkmp_interrupt()
4029 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); in enable_loopback()
4047 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); in enable_loopback()
4302 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) { in tx_load_fifo()
4396 RegValue |= BIT1; in async_mode()
[all …]
/linux-3.4.99/drivers/staging/keucr/
Dsmilecc.c47 #define BIT1 0x02 macro
/linux-3.4.99/include/linux/
Dsynclink.h19 #define BIT1 0x0002 macro
/linux-3.4.99/drivers/char/pcmcia/
Dsynclink_cs.c303 #define IRQ_OVERRUN BIT1 // receive frame overflow
310 #define CTS BIT1 // CTS state
313 #define PVR_DSR BIT1
675 #define CMD_TXEOM BIT1 // transmit end message
1180 if (gis & (BIT1 + BIT0)) { in mgslpc_isr()
1232 if (pis & BIT1) in mgslpc_isr()
3005 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0); in loopback_enable()
3140 val |= BIT1; in hdlc_mode()
3159 val |= BIT2 + BIT1; in hdlc_mode()
3585 if (read_reg(info, CHB + STAR) & BIT1) in get_signals()

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