Searched refs:BAR0 (Results 1 – 7 of 7) sorted by relevance
| /linux-3.4.99/sound/pci/lola/ |
| D | lola.c | 107 lola_writew(chip, BAR0, CORBWP, wp); in corb_send_verb()
128 wp = lola_readw(chip, BAR0, RIRBWP); in lola_update_rirb()
278 rbsts = lola_readb(chip, BAR0, RIRBSTS); in lola_interrupt()
281 lola_writeb(chip, BAR0, RIRBSTS, rbsts); in lola_interrupt()
282 rbsts = lola_readb(chip, BAR0, CORBSTS); in lola_interrupt()
285 lola_writeb(chip, BAR0, CORBSTS, rbsts); in lola_interrupt()
311 unsigned int gctl = lola_readl(chip, BAR0, GCTL); in reset_controller()
321 lola_writel(chip, BAR0, GCTL, LOLA_GCTL_RESET); in reset_controller()
325 gctl = lola_readl(chip, BAR0, GCTL); in reset_controller()
377 lola_writeb(chip, BAR0, RIRBCTL, 0); in setup_corb_rirb()
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| D | lola_proc.c | 180 readl(chip->bar[BAR0].remap_addr + i)); in lola_proc_regs_read()
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| D | lola.h | 386 #define BAR0 0 macro
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| /linux-3.4.99/Documentation/scsi/ |
| D | hptiop.txt | 6 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2:
8 BAR0 offset Register
25 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
27 BAR0 offset Register
40 For Marvell IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
42 BAR0 offset Register
71 relative to the IOP BAR0.
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| D | ChangeLog.lpfc | 1085 CONFIG_PORT uses HBA's view of its BAR0.
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| /linux-3.4.99/Documentation/misc-devices/ |
| D | spear-pcie-gadget.txt | 78 program BAR0 size as 1MB
84 Program BAR0 Address as DDR (0x2100000). This is the physical address of
87 as BAR0 address then when this device will be connected to a host, it will be
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| /linux-3.4.99/Documentation/video4linux/cx2341x/ |
| D | fw-memory.txt | 19 The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0
21 address held in BAR0.
40 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
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