1 /*
2  * DO NOT EDIT THIS FILE
3  * This file is under version control at
4  *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5  * and can be replaced with that version at any time
6  * DO NOT EDIT THIS FILE
7  *
8  * Copyright 2004-2011 Analog Devices Inc.
9  * Licensed under the ADI BSD license.
10  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11  */
12 
13 /* This file should be up to date with:
14  *  - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
15  */
16 
17 #ifndef _MACH_ANOMALY_H_
18 #define _MACH_ANOMALY_H_
19 
20 /* We do not support 0.0 or 0.1 silicon - sorry */
21 #if __SILICON_REVISION__ < 2
22 # error will not work on BF548 silicon version 0.0, or 0.1
23 #endif
24 
25 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
26 #define ANOMALY_05000074 (1)
27 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
28 #define ANOMALY_05000119 (1)
29 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30 #define ANOMALY_05000122 (1)
31 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
32 #define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
33 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
34 #define ANOMALY_05000245 (1)
35 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
36 #define ANOMALY_05000265 (1)
37 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
38 #define ANOMALY_05000272 (1)
39 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
40 #define ANOMALY_05000310 (1)
41 /* FIFO Boot Mode Not Functional */
42 #define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
43 /* bfrom_SysControl() Firmware Function Performs Improper System Reset */
44 /*
45  * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
46  *       shows that the fix itself does not cover all cases.
47  */
48 #define ANOMALY_05000353 (1)
49 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
50 #define ANOMALY_05000357 (1)
51 /* External Memory Read Access Hangs Core With PLL Bypass */
52 #define ANOMALY_05000360 (1)
53 /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
54 #define ANOMALY_05000365 (1)
55 /* Addressing Conflict between Boot ROM and Asynchronous Memory */
56 #define ANOMALY_05000369 (1)
57 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
58 #define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
59 /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
60 #define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
61 /* 16-Bit NAND FLASH Boot Mode Is Not Functional */
62 #define ANOMALY_05000379 (1)
63 /* Lockbox SESR Disallows Certain User Interrupts */
64 #define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
65 /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
66 #define ANOMALY_05000405 (1)
67 /* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
68 #define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
69 /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
70 #define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
71 /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
72 #define ANOMALY_05000408 (1)
73 /* Lockbox firmware leaves MDMA0 channel enabled */
74 #define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
75 /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
76 #define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
77 /* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
78 #define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
79 /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
80 #define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
81 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
82 #define ANOMALY_05000416 (1)
83 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
84 #define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
85 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
86 #define ANOMALY_05000426 (1)
87 /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
88 #define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
89 /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
90 #define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
91 /* Software System Reset Corrupts PLL_LOCKCNT Register */
92 #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
93 /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
94 #define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
95 /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
96 #define ANOMALY_05000434 (1)
97 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
98 #define ANOMALY_05000443 (1)
99 /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
100 #define ANOMALY_05000446 (1)
101 /* UART IrDA Receiver Fails on Extended Bit Pulses */
102 #define ANOMALY_05000447 (1)
103 /* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
104 #define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
105 /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
106 #define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
107 /* USB DMA Short Packet Data Corruption */
108 #define ANOMALY_05000450 (1)
109 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
110 #define ANOMALY_05000456 (1)
111 /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
112 #define ANOMALY_05000457 (1)
113 /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
114 #define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
115 /* False Hardware Error when RETI Points to Invalid Memory */
116 #define ANOMALY_05000461 (1)
117 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
118 #define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
119 /* USB DMA RX Data Corruption */
120 #define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
121 /* USB TX DMA Hang */
122 #define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
123 /* USB Rx DMA Hang */
124 #define ANOMALY_05000465 (1)
125 /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
126 #define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
127 /* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
128 #define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
129 /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
130 #define ANOMALY_05000473 (1)
131 /* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
132 #define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
133 /* TESTSET Instruction Cannot Be Interrupted */
134 #define ANOMALY_05000477 (1)
135 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
136 #define ANOMALY_05000481 (1)
137 /* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
138 #define ANOMALY_05000483 (1)
139 /* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
140 #define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
141 /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
142 #define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
143 /* PLL May Latch Incorrect Values Coming Out of Reset */
144 #define ANOMALY_05000489 (1)
145 /* SPI Master Boot Can Fail Under Certain Conditions */
146 #define ANOMALY_05000490 (1)
147 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
148 #define ANOMALY_05000491 (1)
149 /* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
150 #define ANOMALY_05000494 (1)
151 /* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
152 #define ANOMALY_05000498 (1)
153 /* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
154 #define ANOMALY_05000500 (1)
155 /* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
156 #define ANOMALY_05000501 (1)
157 /* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
158 #define ANOMALY_05000502 (1)
159 
160 /*
161  * These anomalies have been "phased" out of analog.com anomaly sheets and are
162  * here to show running on older silicon just isn't feasible.
163  */
164 
165 /* False Hardware Error when ISR Context Is Not Restored */
166 #define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
167 /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
168 #define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
169 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
170 #define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
171 /* TWI Slave Boot Mode Is Not Functional */
172 #define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
173 /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
174 #define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
175 /* Incorrect Access of OTP_STATUS During otp_write() Function */
176 #define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
177 /* Synchronous Burst Flash Boot Mode Is Not Functional */
178 #define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
179 /* Host DMA Boot Modes Are Not Functional */
180 #define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
181 /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
182 #define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
183 /* Inadequate Rotary Debounce Logic Duration */
184 #define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
185 /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
186 #define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
187 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
188 #define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
189 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
190 #define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
191 /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
192 #define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
193 /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
194 #define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
195 /* USB Calibration Value Is Not Initialized */
196 #define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
197 /* USB Calibration Value to use */
198 #define ANOMALY_05000346_value 0x5411
199 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */
200 #define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
201 /* Data Lost when Core Reads SDH Data FIFO */
202 #define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
203 /* PLL Status Register Is Inaccurate */
204 #define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
205 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
206 #define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
207 /* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
208 #define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
209 /* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
210 #define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
211 /* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
212 #define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
213 /* USB DP/DM Data Pins May Lose State When Entering Hibernate */
214 #define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
215 /* 8-Bit NAND Flash Boot Mode Not Functional */
216 #define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
217 /* Boot from OTP Memory Not Functional */
218 #define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
219 /* bfrom_SysControl() Firmware Routine Not Functional */
220 #define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
221 /* Programmable Preboot Settings Not Functional */
222 #define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
223 /* CRC32 Checksum Support Not Functional */
224 #define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
225 /* Reset Vector Must Not Be in SDRAM Memory Space */
226 #define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
227 /* Changed Meaning of BCODE Field in SYSCR Register */
228 #define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
229 /* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
230 #define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
231 /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
232 #define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
233 /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
234 #define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
235 /* Log Buffer Not Functional */
236 #define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
237 /* Hook Routine Not Functional */
238 #define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
239 /* Header Indirect Bit Not Functional */
240 #define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
241 /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
242 #define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
243 /* OTP Write Accesses Not Supported */
244 #define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
245 /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
246 #define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
247 
248 /* Anomalies that don't exist on this proc */
249 #define ANOMALY_05000099 (0)
250 #define ANOMALY_05000120 (0)
251 #define ANOMALY_05000125 (0)
252 #define ANOMALY_05000149 (0)
253 #define ANOMALY_05000158 (0)
254 #define ANOMALY_05000171 (0)
255 #define ANOMALY_05000179 (0)
256 #define ANOMALY_05000182 (0)
257 #define ANOMALY_05000183 (0)
258 #define ANOMALY_05000189 (0)
259 #define ANOMALY_05000198 (0)
260 #define ANOMALY_05000202 (0)
261 #define ANOMALY_05000215 (0)
262 #define ANOMALY_05000219 (0)
263 #define ANOMALY_05000227 (0)
264 #define ANOMALY_05000230 (0)
265 #define ANOMALY_05000231 (0)
266 #define ANOMALY_05000233 (0)
267 #define ANOMALY_05000234 (0)
268 #define ANOMALY_05000242 (0)
269 #define ANOMALY_05000244 (0)
270 #define ANOMALY_05000248 (0)
271 #define ANOMALY_05000250 (0)
272 #define ANOMALY_05000254 (0)
273 #define ANOMALY_05000257 (0)
274 #define ANOMALY_05000261 (0)
275 #define ANOMALY_05000263 (0)
276 #define ANOMALY_05000266 (0)
277 #define ANOMALY_05000273 (0)
278 #define ANOMALY_05000274 (0)
279 #define ANOMALY_05000278 (0)
280 #define ANOMALY_05000283 (0)
281 #define ANOMALY_05000287 (0)
282 #define ANOMALY_05000301 (0)
283 #define ANOMALY_05000305 (0)
284 #define ANOMALY_05000307 (0)
285 #define ANOMALY_05000311 (0)
286 #define ANOMALY_05000315 (0)
287 #define ANOMALY_05000323 (0)
288 #define ANOMALY_05000362 (1)
289 #define ANOMALY_05000363 (0)
290 #define ANOMALY_05000364 (0)
291 #define ANOMALY_05000380 (0)
292 #define ANOMALY_05000400 (0)
293 #define ANOMALY_05000402 (0)
294 #define ANOMALY_05000412 (0)
295 #define ANOMALY_05000432 (0)
296 #define ANOMALY_05000435 (0)
297 #define ANOMALY_05000440 (0)
298 #define ANOMALY_05000475 (0)
299 #define ANOMALY_05000480 (0)
300 
301 #endif
302