1 /* 2 * AD9832 SPI DDS driver 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 #ifndef IIO_DDS_AD9832_H_ 9 #define IIO_DDS_AD9832_H_ 10 11 /* Registers */ 12 13 #define AD9832_FREQ0LL 0x0 14 #define AD9832_FREQ0HL 0x1 15 #define AD9832_FREQ0LM 0x2 16 #define AD9832_FREQ0HM 0x3 17 #define AD9832_FREQ1LL 0x4 18 #define AD9832_FREQ1HL 0x5 19 #define AD9832_FREQ1LM 0x6 20 #define AD9832_FREQ1HM 0x7 21 #define AD9832_PHASE0L 0x8 22 #define AD9832_PHASE0H 0x9 23 #define AD9832_PHASE1L 0xA 24 #define AD9832_PHASE1H 0xB 25 #define AD9832_PHASE2L 0xC 26 #define AD9832_PHASE2H 0xD 27 #define AD9832_PHASE3L 0xE 28 #define AD9832_PHASE3H 0xF 29 30 #define AD9832_PHASE_SYM 0x10 31 #define AD9832_FREQ_SYM 0x11 32 #define AD9832_PINCTRL_EN 0x12 33 #define AD9832_OUTPUT_EN 0x13 34 35 /* Command Control Bits */ 36 37 #define AD9832_CMD_PHA8BITSW 0x1 38 #define AD9832_CMD_PHA16BITSW 0x0 39 #define AD9832_CMD_FRE8BITSW 0x3 40 #define AD9832_CMD_FRE16BITSW 0x2 41 #define AD9832_CMD_FPSELECT 0x6 42 #define AD9832_CMD_SYNCSELSRC 0x8 43 #define AD9832_CMD_SLEEPRESCLR 0xC 44 45 #define AD9832_FREQ (1 << 11) 46 #define AD9832_PHASE(x) (((x) & 3) << 9) 47 #define AD9832_SYNC (1 << 13) 48 #define AD9832_SELSRC (1 << 12) 49 #define AD9832_SLEEP (1 << 13) 50 #define AD9832_RESET (1 << 12) 51 #define AD9832_CLR (1 << 11) 52 #define CMD_SHIFT 12 53 #define ADD_SHIFT 8 54 #define AD9832_FREQ_BITS 32 55 #define AD9832_PHASE_BITS 12 56 #define RES_MASK(bits) ((1 << (bits)) - 1) 57 58 /** 59 * struct ad9832_state - driver instance specific data 60 * @spi: spi_device 61 * @reg: supply regulator 62 * @mclk: external master clock 63 * @ctrl_fp: cached frequency/phase control word 64 * @ctrl_ss: cached sync/selsrc control word 65 * @ctrl_src: cached sleep/reset/clr word 66 * @xfer: default spi transfer 67 * @msg: default spi message 68 * @freq_xfer: tuning word spi transfer 69 * @freq_msg: tuning word spi message 70 * @phase_xfer: tuning word spi transfer 71 * @phase_msg: tuning word spi message 72 * @data: spi transmit buffer 73 * @phase_data: tuning word spi transmit buffer 74 * @freq_data: tuning word spi transmit buffer 75 */ 76 77 struct ad9832_state { 78 struct spi_device *spi; 79 struct regulator *reg; 80 unsigned long mclk; 81 unsigned short ctrl_fp; 82 unsigned short ctrl_ss; 83 unsigned short ctrl_src; 84 struct spi_transfer xfer; 85 struct spi_message msg; 86 struct spi_transfer freq_xfer[4]; 87 struct spi_message freq_msg; 88 struct spi_transfer phase_xfer[2]; 89 struct spi_message phase_msg; 90 /* 91 * DMA (thus cache coherency maintenance) requires the 92 * transfer buffers to live in their own cache lines. 93 */ 94 union { 95 unsigned short freq_data[4]____cacheline_aligned; 96 unsigned short phase_data[2]; 97 unsigned short data; 98 }; 99 }; 100 101 /* 102 * TODO: struct ad9832_platform_data needs to go into include/linux/iio 103 */ 104 105 /** 106 * struct ad9832_platform_data - platform specific information 107 * @mclk: master clock in Hz 108 * @freq0: power up freq0 tuning word in Hz 109 * @freq1: power up freq1 tuning word in Hz 110 * @phase0: power up phase0 value [0..4095] correlates with 0..2PI 111 * @phase1: power up phase1 value [0..4095] correlates with 0..2PI 112 * @phase2: power up phase2 value [0..4095] correlates with 0..2PI 113 * @phase3: power up phase3 value [0..4095] correlates with 0..2PI 114 */ 115 116 struct ad9832_platform_data { 117 unsigned long mclk; 118 unsigned long freq0; 119 unsigned long freq1; 120 unsigned short phase0; 121 unsigned short phase1; 122 unsigned short phase2; 123 unsigned short phase3; 124 }; 125 126 #endif /* IIO_DDS_AD9832_H_ */ 127