1 /*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 */
7 #ifndef MFD_AB8500_H
8 #define MFD_AB8500_H
9
10 #include <linux/mutex.h>
11
12 struct device;
13
14 /*
15 * AB IC versions
16 *
17 * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
18 * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
19 * print of version string.
20 */
21 enum ab8500_version {
22 AB8500_VERSION_AB8500 = 0x0,
23 AB8500_VERSION_AB8505 = 0x1,
24 AB8500_VERSION_AB9540 = 0x2,
25 AB8500_VERSION_AB8540 = 0x3,
26 AB8500_VERSION_UNDEFINED,
27 };
28
29 /* AB8500 CIDs*/
30 #define AB8500_CUTEARLY 0x00
31 #define AB8500_CUT1P0 0x10
32 #define AB8500_CUT1P1 0x11
33 #define AB8500_CUT2P0 0x20
34 #define AB8500_CUT3P0 0x30
35 #define AB8500_CUT3P3 0x33
36
37 /*
38 * AB8500 bank addresses
39 */
40 #define AB8500_SYS_CTRL1_BLOCK 0x1
41 #define AB8500_SYS_CTRL2_BLOCK 0x2
42 #define AB8500_REGU_CTRL1 0x3
43 #define AB8500_REGU_CTRL2 0x4
44 #define AB8500_USB 0x5
45 #define AB8500_TVOUT 0x6
46 #define AB8500_DBI 0x7
47 #define AB8500_ECI_AV_ACC 0x8
48 #define AB8500_RESERVED 0x9
49 #define AB8500_GPADC 0xA
50 #define AB8500_CHARGER 0xB
51 #define AB8500_GAS_GAUGE 0xC
52 #define AB8500_AUDIO 0xD
53 #define AB8500_INTERRUPT 0xE
54 #define AB8500_RTC 0xF
55 #define AB8500_MISC 0x10
56 #define AB8500_DEVELOPMENT 0x11
57 #define AB8500_DEBUG 0x12
58 #define AB8500_PROD_TEST 0x13
59 #define AB8500_OTP_EMUL 0x15
60
61 /*
62 * Interrupts
63 * Values used to index into array ab8500_irq_regoffset[] defined in
64 * drivers/mdf/ab8500-core.c
65 */
66 /* Definitions for AB8500 and AB9540 */
67 /* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
68 #define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
69 #define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */
70 #define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */
71 #define AB8500_INT_TEMP_WARM 3
72 #define AB8500_INT_PON_KEY2DB_F 4
73 #define AB8500_INT_PON_KEY2DB_R 5
74 #define AB8500_INT_PON_KEY1DB_F 6
75 #define AB8500_INT_PON_KEY1DB_R 7
76 /* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
77 #define AB8500_INT_BATT_OVV 8
78 #define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */
79 #define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */
80 #define AB8500_INT_VBUS_DET_F 14
81 #define AB8500_INT_VBUS_DET_R 15
82 /* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
83 #define AB8500_INT_VBUS_CH_DROP_END 16
84 #define AB8500_INT_RTC_60S 17
85 #define AB8500_INT_RTC_ALARM 18
86 #define AB8500_INT_BAT_CTRL_INDB 20
87 #define AB8500_INT_CH_WD_EXP 21
88 #define AB8500_INT_VBUS_OVV 22
89 #define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */
90 /* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
91 #define AB8500_INT_CCN_CONV_ACC 24
92 #define AB8500_INT_INT_AUD 25
93 #define AB8500_INT_CCEOC 26
94 #define AB8500_INT_CC_INT_CALIB 27
95 #define AB8500_INT_LOW_BAT_F 28
96 #define AB8500_INT_LOW_BAT_R 29
97 #define AB8500_INT_BUP_CHG_NOT_OK 30
98 #define AB8500_INT_BUP_CHG_OK 31
99 /* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
100 #define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */
101 #define AB8500_INT_ACC_DETECT_1DB_F 33
102 #define AB8500_INT_ACC_DETECT_1DB_R 34
103 #define AB8500_INT_ACC_DETECT_22DB_F 35
104 #define AB8500_INT_ACC_DETECT_22DB_R 36
105 #define AB8500_INT_ACC_DETECT_21DB_F 37
106 #define AB8500_INT_ACC_DETECT_21DB_R 38
107 #define AB8500_INT_GP_SW_ADC_CONV_END 39
108 /* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
109 #define AB8500_INT_GPIO6R 40 /* not 8505/9540 */
110 #define AB8500_INT_GPIO7R 41 /* not 8505/9540 */
111 #define AB8500_INT_GPIO8R 42 /* not 8505/9540 */
112 #define AB8500_INT_GPIO9R 43 /* not 8505/9540 */
113 #define AB8500_INT_GPIO10R 44
114 #define AB8500_INT_GPIO11R 45
115 #define AB8500_INT_GPIO12R 46 /* not 8505 */
116 #define AB8500_INT_GPIO13R 47
117 /* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
118 #define AB8500_INT_GPIO24R 48 /* not 8505 */
119 #define AB8500_INT_GPIO25R 49 /* not 8505 */
120 #define AB8500_INT_GPIO36R 50 /* not 8505/9540 */
121 #define AB8500_INT_GPIO37R 51 /* not 8505/9540 */
122 #define AB8500_INT_GPIO38R 52 /* not 8505/9540 */
123 #define AB8500_INT_GPIO39R 53 /* not 8505/9540 */
124 #define AB8500_INT_GPIO40R 54
125 #define AB8500_INT_GPIO41R 55
126 /* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
127 #define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
128 #define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
129 #define AB8500_INT_GPIO8F 58 /* not 8505/9540 */
130 #define AB8500_INT_GPIO9F 59 /* not 8505/9540 */
131 #define AB8500_INT_GPIO10F 60
132 #define AB8500_INT_GPIO11F 61
133 #define AB8500_INT_GPIO12F 62 /* not 8505 */
134 #define AB8500_INT_GPIO13F 63
135 /* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
136 #define AB8500_INT_GPIO24F 64 /* not 8505 */
137 #define AB8500_INT_GPIO25F 65 /* not 8505 */
138 #define AB8500_INT_GPIO36F 66 /* not 8505/9540 */
139 #define AB8500_INT_GPIO37F 67 /* not 8505/9540 */
140 #define AB8500_INT_GPIO38F 68 /* not 8505/9540 */
141 #define AB8500_INT_GPIO39F 69 /* not 8505/9540 */
142 #define AB8500_INT_GPIO40F 70
143 #define AB8500_INT_GPIO41F 71
144 /* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
145 #define AB8500_INT_ADP_SOURCE_ERROR 72
146 #define AB8500_INT_ADP_SINK_ERROR 73
147 #define AB8500_INT_ADP_PROBE_PLUG 74
148 #define AB8500_INT_ADP_PROBE_UNPLUG 75
149 #define AB8500_INT_ADP_SENSE_OFF 76
150 #define AB8500_INT_USB_PHY_POWER_ERR 78
151 #define AB8500_INT_USB_LINK_STATUS 79
152 /* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
153 #define AB8500_INT_BTEMP_LOW 80
154 #define AB8500_INT_BTEMP_LOW_MEDIUM 81
155 #define AB8500_INT_BTEMP_MEDIUM_HIGH 82
156 #define AB8500_INT_BTEMP_HIGH 83
157 /* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
158 #define AB8500_INT_SRP_DETECT 88
159 #define AB8500_INT_USB_CHARGER_NOT_OKR 89
160 #define AB8500_INT_ID_WAKEUP_R 90
161 #define AB8500_INT_ID_DET_R1R 92
162 #define AB8500_INT_ID_DET_R2R 93
163 #define AB8500_INT_ID_DET_R3R 94
164 #define AB8500_INT_ID_DET_R4R 95
165 /* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
166 #define AB8500_INT_ID_WAKEUP_F 96
167 #define AB8500_INT_ID_DET_R1F 98
168 #define AB8500_INT_ID_DET_R2F 99
169 #define AB8500_INT_ID_DET_R3F 100
170 #define AB8500_INT_ID_DET_R4F 101
171 #define AB8500_INT_CHAUTORESTARTAFTSEC 102
172 #define AB8500_INT_CHSTOPBYSEC 103
173 /* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
174 #define AB8500_INT_USB_CH_TH_PROT_F 104
175 #define AB8500_INT_USB_CH_TH_PROT_R 105
176 #define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
177 #define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
178 #define AB8500_INT_CHCURLIMNOHSCHIRP 109
179 #define AB8500_INT_CHCURLIMHSCHIRP 110
180 #define AB8500_INT_XTAL32K_KO 111
181
182 /* Definitions for AB9540 */
183 /* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
184 #define AB9540_INT_GPIO50R 113
185 #define AB9540_INT_GPIO51R 114 /* not 8505 */
186 #define AB9540_INT_GPIO52R 115
187 #define AB9540_INT_GPIO53R 116
188 #define AB9540_INT_GPIO54R 117 /* not 8505 */
189 #define AB9540_INT_IEXT_CH_RF_BFN_R 118
190 #define AB9540_INT_IEXT_CH_RF_BFN_F 119
191 /* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
192 #define AB9540_INT_GPIO50F 121
193 #define AB9540_INT_GPIO51F 122 /* not 8505 */
194 #define AB9540_INT_GPIO52F 123
195 #define AB9540_INT_GPIO53F 124
196 #define AB9540_INT_GPIO54F 125 /* not 8505 */
197
198 /*
199 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
200 * entire platform. This is a "compile time" constant so this must be set to
201 * the largest possible value that may be encountered with different AB SOCs.
202 * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
203 * which is larger.
204 */
205 #define AB8500_NR_IRQS 112
206 #define AB8505_NR_IRQS 128
207 #define AB9540_NR_IRQS 128
208 /* This is set to the roof of any AB8500 chip variant IRQ counts */
209 #define AB8500_MAX_NR_IRQS AB9540_NR_IRQS
210
211 #define AB8500_NUM_IRQ_REGS 14
212 #define AB9540_NUM_IRQ_REGS 17
213
214 /**
215 * struct ab8500 - ab8500 internal structure
216 * @dev: parent device
217 * @lock: read/write operations lock
218 * @irq_lock: genirq bus lock
219 * @irq: irq line
220 * @version: chip version id (e.g. ab8500 or ab9540)
221 * @chip_id: chip revision id
222 * @write: register write
223 * @write_masked: masked register write
224 * @read: register read
225 * @rx_buf: rx buf for SPI
226 * @tx_buf: tx buf for SPI
227 * @mask: cache of IRQ regs for bus lock
228 * @oldmask: cache of previous IRQ regs for bus lock
229 * @mask_size: Actual number of valid entries in mask[], oldmask[] and
230 * irq_reg_offset
231 * @irq_reg_offset: Array of offsets into IRQ registers
232 */
233 struct ab8500 {
234 struct device *dev;
235 struct mutex lock;
236 struct mutex irq_lock;
237
238 int irq_base;
239 int irq;
240 enum ab8500_version version;
241 u8 chip_id;
242
243 int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
244 int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
245 int (*read)(struct ab8500 *ab8500, u16 addr);
246
247 unsigned long tx_buf[4];
248 unsigned long rx_buf[4];
249
250 u8 *mask;
251 u8 *oldmask;
252 int mask_size;
253 const int *irq_reg_offset;
254 };
255
256 struct regulator_reg_init;
257 struct regulator_init_data;
258 struct ab8500_gpio_platform_data;
259
260 /**
261 * struct ab8500_platform_data - AB8500 platform data
262 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
263 * @init: board-specific initialization after detection of ab8500
264 * @num_regulator_reg_init: number of regulator init registers
265 * @regulator_reg_init: regulator init registers
266 * @num_regulator: number of regulators
267 * @regulator: machine-specific constraints for regulators
268 */
269 struct ab8500_platform_data {
270 int irq_base;
271 void (*init) (struct ab8500 *);
272 int num_regulator_reg_init;
273 struct ab8500_regulator_reg_init *regulator_reg_init;
274 int num_regulator;
275 struct regulator_init_data *regulator;
276 struct ab8500_gpio_platform_data *gpio;
277 };
278
279 extern int __devinit ab8500_init(struct ab8500 *ab8500,
280 enum ab8500_version version);
281 extern int __devexit ab8500_exit(struct ab8500 *ab8500);
282
is_ab8500(struct ab8500 * ab)283 static inline int is_ab8500(struct ab8500 *ab)
284 {
285 return ab->version == AB8500_VERSION_AB8500;
286 }
287
is_ab8505(struct ab8500 * ab)288 static inline int is_ab8505(struct ab8500 *ab)
289 {
290 return ab->version == AB8500_VERSION_AB8505;
291 }
292
is_ab9540(struct ab8500 * ab)293 static inline int is_ab9540(struct ab8500 *ab)
294 {
295 return ab->version == AB8500_VERSION_AB9540;
296 }
297
is_ab8540(struct ab8500 * ab)298 static inline int is_ab8540(struct ab8500 *ab)
299 {
300 return ab->version == AB8500_VERSION_AB8540;
301 }
302
303 /* exclude also ab8505, ab9540... */
is_ab8500_1p0_or_earlier(struct ab8500 * ab)304 static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
305 {
306 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
307 }
308
309 /* exclude also ab8505, ab9540... */
is_ab8500_1p1_or_earlier(struct ab8500 * ab)310 static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
311 {
312 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
313 }
314
315 /* exclude also ab8505, ab9540... */
is_ab8500_2p0_or_earlier(struct ab8500 * ab)316 static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
317 {
318 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
319 }
320
321 /* exclude also ab8505, ab9540... */
is_ab8500_2p0(struct ab8500 * ab)322 static inline int is_ab8500_2p0(struct ab8500 *ab)
323 {
324 return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
325 }
326
327 #endif /* MFD_AB8500_H */
328