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Searched refs:wr32 (Results 1 – 8 of 8) sorted by relevance

/linux-2.6.39/drivers/net/igb/
De1000_82575.c304 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_invariants_82575()
523 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); in igb_get_phy_id_82575()
557 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_phy_id_82575()
752 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_82575()
777 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_82575()
866 wr32(E1000_PCS_CFG0, reg); in igb_power_up_serdes_link_82575()
871 wr32(E1000_CTRL_EXT, reg); in igb_power_up_serdes_link_82575()
952 wr32(E1000_PCS_CFG0, reg); in igb_shutdown_serdes_link_82575()
957 wr32(E1000_CTRL_EXT, reg); in igb_shutdown_serdes_link_82575()
992 wr32(E1000_IMC, 0xffffffff); in igb_reset_hw_82575()
[all …]
Digb_main.c862 wr32(E1000_CTRL_EXT, tmp); in igb_configure_msix()
876 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | in igb_configure_msix()
884 wr32(E1000_IVAR_MISC, tmp); in igb_configure_msix()
1053 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); in igb_set_interrupt_capability()
1300 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1301 wr32(E1000_EIMC, adapter->eims_enable_mask); in igb_irq_disable()
1303 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1306 wr32(E1000_IAM, 0); in igb_irq_disable()
1307 wr32(E1000_IMC, ~0); in igb_irq_disable()
1329 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); in igb_irq_enable()
[all …]
De1000_mac.c268 wr32(E1000_RAL(index), rar_low); in igb_rar_set()
270 wr32(E1000_RAH(index), rar_high); in igb_rar_set()
589 wr32(E1000_FCT, FLOW_CONTROL_TYPE); in igb_setup_link()
590 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); in igb_setup_link()
591 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); in igb_setup_link()
593 wr32(E1000_FCTTV, hw->fc.pause_time); in igb_setup_link()
618 wr32(E1000_TCTL, tctl); in igb_config_collision_dist()
654 wr32(E1000_FCRTL, fcrtl); in igb_set_fc_watermarks()
655 wr32(E1000_FCRTH, fcrth); in igb_set_fc_watermarks()
758 wr32(E1000_CTRL, ctrl); in igb_force_mac_fc()
[all …]
De1000_nvm.c44 wr32(E1000_EECD, *eecd); in igb_raise_eec_clk()
59 wr32(E1000_EECD, *eecd); in igb_lower_eec_clk()
90 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
102 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
189 wr32(E1000_EECD, eecd | E1000_EECD_REQ); in igb_acquire_nvm()
202 wr32(E1000_EECD, eecd); in igb_acquire_nvm()
224 wr32(E1000_EECD, eecd); in igb_standby_nvm()
228 wr32(E1000_EECD, eecd); in igb_standby_nvm()
266 wr32(E1000_EECD, eecd); in igb_release_nvm()
287 wr32(E1000_EECD, eecd); in igb_ready_nvm_eeprom()
[all …]
De1000_mbx.c251 wr32(E1000_MBVFICR, mask); in igb_check_for_bit_pf()
309 wr32(E1000_VFLRE, (1 << vf_number)); in igb_check_for_rst_pf()
330 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU); in igb_obtain_mbx_lock_pf()
369 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS); in igb_write_mbx_pf()
406 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK); in igb_read_mbx_pf()
Digb_ethtool.c1082 wr32(reg, (_test[pat] & write)); in reg_pattern_test()
1101 wr32(reg, write & mask); in reg_set_and_check()
1159 wr32(E1000_STATUS, toggle); in igb_reg_test()
1168 wr32(E1000_STATUS, before); in igb_reg_test()
1285 wr32(E1000_IMC, ~0); in igb_intr_test()
1325 wr32(E1000_ICR, ~0); in igb_intr_test()
1327 wr32(E1000_IMC, mask); in igb_intr_test()
1328 wr32(E1000_ICS, mask); in igb_intr_test()
1346 wr32(E1000_ICR, ~0); in igb_intr_test()
1348 wr32(E1000_IMS, mask); in igb_intr_test()
[all …]
De1000_phy.c160 wr32(E1000_MDIC, mdic); in igb_read_phy_reg_mdic()
219 wr32(E1000_MDIC, mdic); in igb_write_phy_reg_mdic()
271 wr32(E1000_I2CCMD, i2ccmd); in igb_read_phy_reg_i2c()
323 wr32(E1000_I2CCMD, i2ccmd); in igb_write_phy_reg_i2c()
1330 wr32(E1000_CTRL, ctrl); in igb_phy_force_speed_duplex_setup()
2013 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); in igb_phy_hw_reset()
2018 wr32(E1000_CTRL, ctrl); in igb_phy_hw_reset()
De1000_regs.h329 #define wr32(reg, value) (writel(value, hw->hw_addr + reg)) macro