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Searched refs:tile (Results 1 – 25 of 32) sorted by relevance

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/linux-2.6.39/drivers/gpu/drm/nouveau/
Dnv10_fb.c18 spin_lock(&dev_priv->tile.lock); in nv20_fb_alloc_tag()
22 spin_unlock(&dev_priv->tile.lock); in nv20_fb_alloc_tag()
32 spin_lock(&dev_priv->tile.lock); in nv20_fb_free_tag()
34 spin_unlock(&dev_priv->tile.lock); in nv20_fb_free_tag()
42 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; in nv10_fb_init_tile_region() local
45 tile->addr = addr; in nv10_fb_init_tile_region()
46 tile->limit = max(1u, addr + size) - 1; in nv10_fb_init_tile_region()
47 tile->pitch = pitch; in nv10_fb_init_tile_region()
57 tile->tag_mem = nv20_fb_alloc_tag(dev, size / 256); in nv10_fb_init_tile_region()
59 if (tile->tag_mem) { in nv10_fb_init_tile_region()
[all …]
Dnv30_fb.c37 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; in nv30_fb_init_tile_region() local
39 tile->addr = addr | 1; in nv30_fb_init_tile_region()
40 tile->limit = max(1u, addr + size) - 1; in nv30_fb_init_tile_region()
41 tile->pitch = pitch; in nv30_fb_init_tile_region()
48 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; in nv30_fb_free_tile_region() local
50 tile->addr = tile->limit = tile->pitch = 0; in nv30_fb_free_tile_region()
Dnv40_fb.c10 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; in nv40_fb_set_tile_region() local
14 nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit); in nv40_fb_set_tile_region()
15 nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch); in nv40_fb_set_tile_region()
16 nv_wr32(dev, NV10_PFB_TILE(i), tile->addr); in nv40_fb_set_tile_region()
20 nv_wr32(dev, NV40_PFB_TLIMIT(i), tile->limit); in nv40_fb_set_tile_region()
21 nv_wr32(dev, NV40_PFB_TSIZE(i), tile->pitch); in nv40_fb_set_tile_region()
22 nv_wr32(dev, NV40_PFB_TILE(i), tile->addr); in nv40_fb_set_tile_region()
Dnouveau_mem.c48 struct nouveau_tile_reg *tile, uint32_t addr, in nv10_mem_update_tile_region() argument
55 int i = tile - dev_priv->tile.reg; in nv10_mem_update_tile_region()
58 nouveau_fence_unref(&tile->fence); in nv10_mem_update_tile_region()
60 if (tile->pitch) in nv10_mem_update_tile_region()
84 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; in nv10_mem_get_tile_region() local
86 spin_lock(&dev_priv->tile.lock); in nv10_mem_get_tile_region()
88 if (!tile->used && in nv10_mem_get_tile_region()
89 (!tile->fence || nouveau_fence_signalled(tile->fence))) in nv10_mem_get_tile_region()
90 tile->used = true; in nv10_mem_get_tile_region()
92 tile = NULL; in nv10_mem_get_tile_region()
[all …]
Dnv40_graph.c211 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; in nv40_graph_set_tile_region() local
220 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_graph_set_tile_region()
221 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_graph_set_tile_region()
222 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr); in nv40_graph_set_tile_region()
223 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_graph_set_tile_region()
224 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_graph_set_tile_region()
225 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_graph_set_tile_region()
229 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_graph_set_tile_region()
230 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_graph_set_tile_region()
231 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr); in nv40_graph_set_tile_region()
[all …]
Dnv20_graph.c518 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; in nv20_graph_set_tile_region() local
520 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv20_graph_set_tile_region()
521 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv20_graph_set_tile_region()
522 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr); in nv20_graph_set_tile_region()
525 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->limit); in nv20_graph_set_tile_region()
527 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->pitch); in nv20_graph_set_tile_region()
529 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->addr); in nv20_graph_set_tile_region()
532 nv_wr32(dev, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv20_graph_set_tile_region()
534 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->zcomp); in nv20_graph_set_tile_region()
Dnv10_graph.c903 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; in nv10_graph_set_tile_region() local
905 nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), tile->limit); in nv10_graph_set_tile_region()
906 nv_wr32(dev, NV10_PGRAPH_TSIZE(i), tile->pitch); in nv10_graph_set_tile_region()
907 nv_wr32(dev, NV10_PGRAPH_TILE(i), tile->addr); in nv10_graph_set_tile_region()
Dnouveau_drv.h114 struct nouveau_tile_reg *tile; member
720 } tile; member
850 struct nouveau_tile_reg *tile,
Dnouveau_bo.c51 nv10_mem_put_tile_region(dev, nvbo->tile, NULL); in nouveau_bo_del_ttm()
958 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); in nouveau_bo_move()
/linux-2.6.39/arch/tile/
DMakefile17 CROSS_COMPILE := $(TILERA_ROOT)/bin/tile-
48 head-y := arch/tile/kernel/head_$(BITS).o
50 libs-y += arch/tile/lib/
54 core-y += arch/tile/
56 core-$(CONFIG_KVM) += arch/tile/kvm/
59 INSTALL_PATH ?= $(TILERA_ROOT)/tile/boot
DKconfig59 # so save boot time by presetting this (particularly useful on tile-sim).
123 default "arch/tile/configs/tile_defconfig" if !TILEGX
124 default "arch/tile/configs/tilegx_defconfig" if TILEGX
363 source "arch/tile/Kconfig.debug"
371 source "arch/tile/kvm/Kconfig"
/linux-2.6.39/arch/tile/kernel/
Dsmp.c214 HV_Coord tile; in ipi_init() local
218 tile.x = cpu_x(cpu); in ipi_init()
219 tile.y = cpu_y(cpu); in ipi_init()
220 if (hv_get_ipi_pte(tile, KERNEL_PL, &pte) != 0) in ipi_init()
DMakefile9 intvec_$(BITS).o regs_$(BITS).o tile-desc_$(BITS).o
Dvmlinux.lds.S10 OUTPUT_ARCH(tile)
/linux-2.6.39/arch/arm/mach-realview/
DKconfig16 Enable support for the Cortex-A9MPCore tile fitted to the
25 Enable support for the ARM11MPCore tile fitted to the Realview(R)
32 Enable support for the ARM11MPCore Revision B tile on the
35 not compatible with other revisions of the ARM11MPCore tile.
/linux-2.6.39/arch/frv/kernel/
Dhead.S554 # split a tile off of the region defined by GR8-GR9
557 # GR4 - IAMPR value representing tile
558 # GR5 - DAMPR value representing tile
559 # GR6 - IAMLR value representing tile
560 # GR7 - DAMLR value representing tile
562 # GR9 region top pointer updated to exclude new tile
Dhead-uc-fr451.S64 movgs gr5,dampr11 ; General I/O tile
67 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
Dhead-uc-fr401.S250 movgs gr5,dampr7 ; General I/O tile
252 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
Dhead-mmu-fr451.S248 movgs gr5,damlr11 ; General I/O tile
/linux-2.6.39/arch/arm/mach-vexpress/
DKconfig5 bool "Versatile Express Cortex-A9x4 tile"
/linux-2.6.39/drivers/hid/
Dhid-picolcd.c314 static int picolcd_fb_send_tile(struct hid_device *hdev, int chip, int tile) in picolcd_fb_send_tile() argument
331 hid_set_field(report1->field[0], 4, 0xb8 | tile); in picolcd_fb_send_tile()
344 tdata = data->fb_vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_send_tile()
359 int chip, int tile) in picolcd_fb_update_tile() argument
363 u8 *vdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_update_tile()
367 const u8 *bdata = bitmap + tile * 256 + chip * 8 + b * 32; in picolcd_fb_update_tile()
375 const u8 *bdata = bitmap + (tile * 256 + chip * 8 + b * 32) * 8; in picolcd_fb_update_tile()
439 int chip, tile, n; in picolcd_fb_update() local
462 for (tile = 0; tile < 8; tile++) in picolcd_fb_update()
464 data->fb_bitmap, data->fb_bpp, chip, tile) || in picolcd_fb_update()
[all …]
/linux-2.6.39/drivers/video/
Dgbefb.c1014 u16 *tile; in gbefb_mmap() local
1030 tile = &gbe_tiles.cpu[offset >> TILE_SHIFT]; in gbefb_mmap()
1036 phys_addr = (((unsigned long) (*tile)) << TILE_SHIFT) + offset; in gbefb_mmap()
1049 tile++; in gbefb_mmap()
/linux-2.6.39/arch/tile/include/hv/
Dhypervisor.h506 int hv_get_ipi_pte(HV_Coord tile, int pl, HV_PTE* pte);
549 HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt);
/linux-2.6.39/drivers/staging/msm/
Dmdp4_overlay.c1213 struct tile_desc tile; in mdp4_overlay_play() local
1215 tile_samsung(&tile); in mdp4_overlay_play()
1216 pipe->srcp1_addr = addr + tile_mem_size(pipe, &tile); in mdp4_overlay_play()
/linux-2.6.39/drivers/net/
DMakefile306 obj-$(CONFIG_TILE_NET) += tile/

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