1 /* vi: ts=8 sw=8 2 * 3 * TI 3410/5052 USB Serial Driver Header 4 * 5 * Copyright (C) 2004 Texas Instruments 6 * 7 * This driver is based on the Linux io_ti driver, which is 8 * Copyright (C) 2000-2002 Inside Out Networks 9 * Copyright (C) 2001-2002 Greg Kroah-Hartman 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * For questions or problems with this driver, contact Texas Instruments 17 * technical support, or Al Borchers <alborchers@steinerpoint.com>, or 18 * Peter Berger <pberger@brimson.com>. 19 */ 20 21 #ifndef _TI_3410_5052_H_ 22 #define _TI_3410_5052_H_ 23 24 /* Configuration ids */ 25 #define TI_BOOT_CONFIG 1 26 #define TI_ACTIVE_CONFIG 2 27 28 /* Vendor and product ids */ 29 #define TI_VENDOR_ID 0x0451 30 #define IBM_VENDOR_ID 0x04b3 31 #define TI_3410_PRODUCT_ID 0x3410 32 #define IBM_4543_PRODUCT_ID 0x4543 33 #define IBM_454B_PRODUCT_ID 0x454b 34 #define IBM_454C_PRODUCT_ID 0x454c 35 #define TI_3410_EZ430_ID 0xF430 /* TI ez430 development tool */ 36 #define TI_5052_BOOT_PRODUCT_ID 0x5052 /* no EEPROM, no firmware */ 37 #define TI_5152_BOOT_PRODUCT_ID 0x5152 /* no EEPROM, no firmware */ 38 #define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */ 39 #define TI_5052_FIRMWARE_PRODUCT_ID 0x505F /* firmware is running */ 40 41 /* Multi-Tech vendor and product ids */ 42 #define MTS_VENDOR_ID 0x06E0 43 #define MTS_GSM_NO_FW_PRODUCT_ID 0xF108 44 #define MTS_CDMA_NO_FW_PRODUCT_ID 0xF109 45 #define MTS_CDMA_PRODUCT_ID 0xF110 46 #define MTS_GSM_PRODUCT_ID 0xF111 47 #define MTS_EDGE_PRODUCT_ID 0xF112 48 #define MTS_MT9234MU_PRODUCT_ID 0xF114 49 #define MTS_MT9234ZBA_PRODUCT_ID 0xF115 50 #define MTS_MT9234ZBAOLD_PRODUCT_ID 0x0319 51 52 /* Commands */ 53 #define TI_GET_VERSION 0x01 54 #define TI_GET_PORT_STATUS 0x02 55 #define TI_GET_PORT_DEV_INFO 0x03 56 #define TI_GET_CONFIG 0x04 57 #define TI_SET_CONFIG 0x05 58 #define TI_OPEN_PORT 0x06 59 #define TI_CLOSE_PORT 0x07 60 #define TI_START_PORT 0x08 61 #define TI_STOP_PORT 0x09 62 #define TI_TEST_PORT 0x0A 63 #define TI_PURGE_PORT 0x0B 64 #define TI_RESET_EXT_DEVICE 0x0C 65 #define TI_WRITE_DATA 0x80 66 #define TI_READ_DATA 0x81 67 #define TI_REQ_TYPE_CLASS 0x82 68 69 /* Module identifiers */ 70 #define TI_I2C_PORT 0x01 71 #define TI_IEEE1284_PORT 0x02 72 #define TI_UART1_PORT 0x03 73 #define TI_UART2_PORT 0x04 74 #define TI_RAM_PORT 0x05 75 76 /* Modem status */ 77 #define TI_MSR_DELTA_CTS 0x01 78 #define TI_MSR_DELTA_DSR 0x02 79 #define TI_MSR_DELTA_RI 0x04 80 #define TI_MSR_DELTA_CD 0x08 81 #define TI_MSR_CTS 0x10 82 #define TI_MSR_DSR 0x20 83 #define TI_MSR_RI 0x40 84 #define TI_MSR_CD 0x80 85 #define TI_MSR_DELTA_MASK 0x0F 86 #define TI_MSR_MASK 0xF0 87 88 /* Line status */ 89 #define TI_LSR_OVERRUN_ERROR 0x01 90 #define TI_LSR_PARITY_ERROR 0x02 91 #define TI_LSR_FRAMING_ERROR 0x04 92 #define TI_LSR_BREAK 0x08 93 #define TI_LSR_ERROR 0x0F 94 #define TI_LSR_RX_FULL 0x10 95 #define TI_LSR_TX_EMPTY 0x20 96 97 /* Line control */ 98 #define TI_LCR_BREAK 0x40 99 100 /* Modem control */ 101 #define TI_MCR_LOOP 0x04 102 #define TI_MCR_DTR 0x10 103 #define TI_MCR_RTS 0x20 104 105 /* Mask settings */ 106 #define TI_UART_ENABLE_RTS_IN 0x0001 107 #define TI_UART_DISABLE_RTS 0x0002 108 #define TI_UART_ENABLE_PARITY_CHECKING 0x0008 109 #define TI_UART_ENABLE_DSR_OUT 0x0010 110 #define TI_UART_ENABLE_CTS_OUT 0x0020 111 #define TI_UART_ENABLE_X_OUT 0x0040 112 #define TI_UART_ENABLE_XA_OUT 0x0080 113 #define TI_UART_ENABLE_X_IN 0x0100 114 #define TI_UART_ENABLE_DTR_IN 0x0800 115 #define TI_UART_DISABLE_DTR 0x1000 116 #define TI_UART_ENABLE_MS_INTS 0x2000 117 #define TI_UART_ENABLE_AUTO_START_DMA 0x4000 118 119 /* Parity */ 120 #define TI_UART_NO_PARITY 0x00 121 #define TI_UART_ODD_PARITY 0x01 122 #define TI_UART_EVEN_PARITY 0x02 123 #define TI_UART_MARK_PARITY 0x03 124 #define TI_UART_SPACE_PARITY 0x04 125 126 /* Stop bits */ 127 #define TI_UART_1_STOP_BITS 0x00 128 #define TI_UART_1_5_STOP_BITS 0x01 129 #define TI_UART_2_STOP_BITS 0x02 130 131 /* Bits per character */ 132 #define TI_UART_5_DATA_BITS 0x00 133 #define TI_UART_6_DATA_BITS 0x01 134 #define TI_UART_7_DATA_BITS 0x02 135 #define TI_UART_8_DATA_BITS 0x03 136 137 /* 232/485 modes */ 138 #define TI_UART_232 0x00 139 #define TI_UART_485_RECEIVER_DISABLED 0x01 140 #define TI_UART_485_RECEIVER_ENABLED 0x02 141 142 /* Pipe transfer mode and timeout */ 143 #define TI_PIPE_MODE_CONTINOUS 0x01 144 #define TI_PIPE_MODE_MASK 0x03 145 #define TI_PIPE_TIMEOUT_MASK 0x7C 146 #define TI_PIPE_TIMEOUT_ENABLE 0x80 147 148 /* Config struct */ 149 struct ti_uart_config { 150 __u16 wBaudRate; 151 __u16 wFlags; 152 __u8 bDataBits; 153 __u8 bParity; 154 __u8 bStopBits; 155 char cXon; 156 char cXoff; 157 __u8 bUartMode; 158 } __attribute__((packed)); 159 160 /* Get port status */ 161 struct ti_port_status { 162 __u8 bCmdCode; 163 __u8 bModuleId; 164 __u8 bErrorCode; 165 __u8 bMSR; 166 __u8 bLSR; 167 } __attribute__((packed)); 168 169 /* Purge modes */ 170 #define TI_PURGE_OUTPUT 0x00 171 #define TI_PURGE_INPUT 0x80 172 173 /* Read/Write data */ 174 #define TI_RW_DATA_ADDR_SFR 0x10 175 #define TI_RW_DATA_ADDR_IDATA 0x20 176 #define TI_RW_DATA_ADDR_XDATA 0x30 177 #define TI_RW_DATA_ADDR_CODE 0x40 178 #define TI_RW_DATA_ADDR_GPIO 0x50 179 #define TI_RW_DATA_ADDR_I2C 0x60 180 #define TI_RW_DATA_ADDR_FLASH 0x70 181 #define TI_RW_DATA_ADDR_DSP 0x80 182 183 #define TI_RW_DATA_UNSPECIFIED 0x00 184 #define TI_RW_DATA_BYTE 0x01 185 #define TI_RW_DATA_WORD 0x02 186 #define TI_RW_DATA_DOUBLE_WORD 0x04 187 188 struct ti_write_data_bytes { 189 __u8 bAddrType; 190 __u8 bDataType; 191 __u8 bDataCounter; 192 __be16 wBaseAddrHi; 193 __be16 wBaseAddrLo; 194 __u8 bData[0]; 195 } __attribute__((packed)); 196 197 struct ti_read_data_request { 198 __u8 bAddrType; 199 __u8 bDataType; 200 __u8 bDataCounter; 201 __be16 wBaseAddrHi; 202 __be16 wBaseAddrLo; 203 } __attribute__((packed)); 204 205 struct ti_read_data_bytes { 206 __u8 bCmdCode; 207 __u8 bModuleId; 208 __u8 bErrorCode; 209 __u8 bData[0]; 210 } __attribute__((packed)); 211 212 /* Interrupt struct */ 213 struct ti_interrupt { 214 __u8 bICode; 215 __u8 bIInfo; 216 } __attribute__((packed)); 217 218 /* Interrupt codes */ 219 #define TI_GET_PORT_FROM_CODE(c) (((c) >> 4) - 3) 220 #define TI_GET_FUNC_FROM_CODE(c) ((c) & 0x0f) 221 #define TI_CODE_HARDWARE_ERROR 0xFF 222 #define TI_CODE_DATA_ERROR 0x03 223 #define TI_CODE_MODEM_STATUS 0x04 224 225 /* Download firmware max packet size */ 226 #define TI_DOWNLOAD_MAX_PACKET_SIZE 64 227 228 /* Firmware image header */ 229 struct ti_firmware_header { 230 __le16 wLength; 231 __u8 bCheckSum; 232 } __attribute__((packed)); 233 234 /* UART addresses */ 235 #define TI_UART1_BASE_ADDR 0xFFA0 /* UART 1 base address */ 236 #define TI_UART2_BASE_ADDR 0xFFB0 /* UART 2 base address */ 237 #define TI_UART_OFFSET_LCR 0x0002 /* UART MCR register offset */ 238 #define TI_UART_OFFSET_MCR 0x0004 /* UART MCR register offset */ 239 240 #endif /* _TI_3410_5052_H_ */ 241