Searched refs:sq_config (Results 1 – 8 of 8) sorted by relevance
| /linux-2.6.39/drivers/gpu/drm/radeon/ |
| D | r600_blit.c | 318 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; in set_default_state() local
444 sq_config = 0; in set_default_state()
446 sq_config = R600_VC_ENABLE; in set_default_state()
448 sq_config |= (R600_DX9_CONSTS | in set_default_state()
483 OUT_RING(sq_config); in set_default_state()
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| D | evergreen_blit_kms.c | 246 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; in set_default_state() local
434 sq_config = 0; in set_default_state()
436 sq_config = VC_ENABLE; in set_default_state()
438 sq_config |= (EXPORT_SRC_C | in set_default_state()
479 radeon_ring_write(rdev, sq_config); in set_default_state()
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| D | r600_blit_kms.c | 278 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; in set_default_state() local
405 sq_config = 0; in set_default_state()
407 sq_config = VC_ENABLE; in set_default_state()
409 sq_config |= (DX9_CONSTS | in set_default_state()
445 radeon_ring_write(rdev, sq_config); in set_default_state()
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| D | r600_cp.c | 742 u32 sq_config; in r600_gfx_init() local
975 sq_config = RADEON_READ(R600_SQ_CONFIG); in r600_gfx_init()
976 sq_config &= ~(R600_PS_PRIO(3) | in r600_gfx_init()
980 sq_config |= (R600_DX9_CONSTS | in r600_gfx_init()
1006 sq_config &= ~R600_VC_ENABLE; in r600_gfx_init()
1052 RADEON_WRITE(R600_SQ_CONFIG, sq_config); in r600_gfx_init()
1369 u32 sq_config; in r700_gfx_init() local
1660 sq_config = RADEON_READ(R600_SQ_CONFIG); in r700_gfx_init()
1661 sq_config &= ~(R600_PS_PRIO(3) | in r700_gfx_init()
1665 sq_config |= (R600_DX9_CONSTS | in r700_gfx_init()
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| D | rv770.c | 590 u32 sq_config; in rv770_gpu_init() local
877 sq_config = RREG32(SQ_CONFIG); in rv770_gpu_init()
878 sq_config &= ~(PS_PRIO(3) | in rv770_gpu_init()
882 sq_config |= (DX9_CONSTS | in rv770_gpu_init()
891 sq_config &= ~VC_ENABLE; in rv770_gpu_init()
893 WREG32(SQ_CONFIG, sq_config); in rv770_gpu_init()
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| D | r600_cs.c | 49 u32 sq_config; member
304 track->sq_config = DX9_CONSTS; in r600_cs_track_init()
950 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1677 if (track->sq_config & DX9_CONSTS) { in r600_packet3_check()
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| D | evergreen.c | 1570 u32 sq_config; in evergreen_gpu_init() local
2023 sq_config = RREG32(SQ_CONFIG); in evergreen_gpu_init()
2024 sq_config &= ~(PS_PRIO(3) | in evergreen_gpu_init()
2028 sq_config |= (VC_ENABLE | in evergreen_gpu_init()
2040 sq_config &= ~VC_ENABLE; in evergreen_gpu_init()
2080 WREG32(SQ_CONFIG, sq_config); in evergreen_gpu_init()
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| D | r600.c | 1517 u32 sq_config; in r600_gpu_init() local
1726 sq_config = RREG32(SQ_CONFIG); in r600_gpu_init()
1727 sq_config &= ~(PS_PRIO(3) | in r600_gpu_init()
1731 sq_config |= (DX9_CONSTS | in r600_gpu_init()
1757 sq_config &= ~VC_ENABLE; in r600_gpu_init()
1803 WREG32(SQ_CONFIG, sq_config); in r600_gpu_init()
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