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Searched refs:speed_cntl (Results 1 – 3 of 3) sorted by relevance

/linux-2.6.39/drivers/gpu/drm/radeon/
Drv770.c1376 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
1409 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
1410 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && in rv770_pcie_gen2_enable()
1411 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in rv770_pcie_gen2_enable()
1422 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
1423 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; in rv770_pcie_gen2_enable()
1424 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); in rv770_pcie_gen2_enable()
1426 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
1427 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; in rv770_pcie_gen2_enable()
1428 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); in rv770_pcie_gen2_enable()
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Devergreen.c3162 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local
3177 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
3178 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || in evergreen_pcie_gen2_enable()
3179 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in evergreen_pcie_gen2_enable()
3185 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
3186 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; in evergreen_pcie_gen2_enable()
3187 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); in evergreen_pcie_gen2_enable()
3189 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
3190 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; in evergreen_pcie_gen2_enable()
3191 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); in evergreen_pcie_gen2_enable()
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Dr600.c3662 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
3703 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
3704 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && in r600_pcie_gen2_enable()
3705 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in r600_pcie_gen2_enable()
3719 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; in r600_pcie_gen2_enable()
3720 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); in r600_pcie_gen2_enable()
3721 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; in r600_pcie_gen2_enable()
3722 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; in r600_pcie_gen2_enable()
3723 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; in r600_pcie_gen2_enable()
3724 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); in r600_pcie_gen2_enable()
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