1 /**************************************************************************
2  * Copyright (c) 2007-2008, Intel Corporation.
3  * All Rights Reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  **************************************************************************/
19 
20 #ifndef _PSB_DRV_H_
21 #define _PSB_DRV_H_
22 
23 #include <linux/version.h>
24 
25 #include <drm/drmP.h>
26 #include "drm_global.h"
27 #include "psb_drm.h"
28 #include "psb_reg.h"
29 #include "psb_intel_drv.h"
30 #include "psb_gtt.h"
31 #include "psb_powermgmt.h"
32 #include "ttm/ttm_object.h"
33 #include "psb_ttm_fence_driver.h"
34 #include "psb_ttm_userobj_api.h"
35 #include "ttm/ttm_bo_driver.h"
36 #include "ttm/ttm_lock.h"
37 
38 /*Append new drm mode definition here, align with libdrm definition*/
39 #define DRM_MODE_SCALE_NO_SCALE   2
40 
41 extern struct ttm_bo_driver psb_ttm_bo_driver;
42 
43 enum {
44 	CHIP_PSB_8108 = 0,
45 	CHIP_PSB_8109 = 1,
46 };
47 
48 /*
49  *Hardware bugfixes
50  */
51 
52 #define DRIVER_NAME "pvrsrvkm"
53 #define DRIVER_DESC "drm driver for the Intel GMA500"
54 #define DRIVER_AUTHOR "Intel Corporation"
55 #define OSPM_PROC_ENTRY "ospm"
56 #define RTPM_PROC_ENTRY "rtpm"
57 #define BLC_PROC_ENTRY "mrst_blc"
58 #define DISPLAY_PROC_ENTRY "display_status"
59 
60 #define PSB_DRM_DRIVER_DATE "2009-03-10"
61 #define PSB_DRM_DRIVER_MAJOR 8
62 #define PSB_DRM_DRIVER_MINOR 1
63 #define PSB_DRM_DRIVER_PATCHLEVEL 0
64 
65 /*
66  *TTM driver private offsets.
67  */
68 
69 #define DRM_PSB_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
70 
71 #define PSB_OBJECT_HASH_ORDER 13
72 #define PSB_FILE_OBJECT_HASH_ORDER 12
73 #define PSB_BO_HASH_ORDER 12
74 
75 #define PSB_VDC_OFFSET		 0x00000000
76 #define PSB_VDC_SIZE		 0x000080000
77 #define MRST_MMIO_SIZE		 0x0000C0000
78 #define MDFLD_MMIO_SIZE          0x000100000
79 #define PSB_SGX_SIZE		 0x8000
80 #define PSB_SGX_OFFSET		 0x00040000
81 #define MRST_SGX_OFFSET		 0x00080000
82 #define PSB_MMIO_RESOURCE	 0
83 #define PSB_GATT_RESOURCE	 2
84 #define PSB_GTT_RESOURCE	 3
85 #define PSB_GMCH_CTRL		 0x52
86 #define PSB_BSM			 0x5C
87 #define _PSB_GMCH_ENABLED	 0x4
88 #define PSB_PGETBL_CTL		 0x2020
89 #define _PSB_PGETBL_ENABLED	 0x00000001
90 #define PSB_SGX_2D_SLAVE_PORT	 0x4000
91 #define PSB_TT_PRIV0_LIMIT	 (256*1024*1024)
92 #define PSB_TT_PRIV0_PLIMIT	 (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
93 #define PSB_NUM_VALIDATE_BUFFERS 2048
94 
95 #define PSB_MEM_MMU_START       0x00000000
96 #define PSB_MEM_TT_START        0xE0000000
97 
98 #define PSB_GL3_CACHE_CTL	0x2100
99 #define PSB_GL3_CACHE_STAT	0x2108
100 
101 /*
102  *Flags for external memory type field.
103  */
104 
105 #define MRST_MSVDX_OFFSET	0x90000	/*MSVDX Base offset */
106 #define PSB_MSVDX_OFFSET	0x50000	/*MSVDX Base offset */
107 /* MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
108 #define PSB_MSVDX_SIZE		0x10000
109 
110 #define LNC_TOPAZ_OFFSET	0xA0000
111 #define PNW_TOPAZ_OFFSET	0xC0000
112 #define PNW_GL3_OFFSET		0xB0000
113 #define LNC_TOPAZ_SIZE		0x10000
114 #define PNW_TOPAZ_SIZE		0x30000 /* PNW VXE285 has two cores */
115 #define PSB_MMU_CACHED_MEMORY	  0x0001	/* Bind to MMU only */
116 #define PSB_MMU_RO_MEMORY	  0x0002	/* MMU RO memory */
117 #define PSB_MMU_WO_MEMORY	  0x0004	/* MMU WO memory */
118 
119 /*
120  *PTE's and PDE's
121  */
122 
123 #define PSB_PDE_MASK		  0x003FFFFF
124 #define PSB_PDE_SHIFT		  22
125 #define PSB_PTE_SHIFT		  12
126 
127 #define PSB_PTE_VALID		  0x0001	/* PTE / PDE valid */
128 #define PSB_PTE_WO		  0x0002	/* Write only */
129 #define PSB_PTE_RO		  0x0004	/* Read only */
130 #define PSB_PTE_CACHED		  0x0008	/* CPU cache coherent */
131 
132 /*
133  *VDC registers and bits
134  */
135 #define PSB_MSVDX_CLOCKGATING	  0x2064
136 #define PSB_TOPAZ_CLOCKGATING	  0x2068
137 #define PSB_HWSTAM		  0x2098
138 #define PSB_INSTPM		  0x20C0
139 #define PSB_INT_IDENTITY_R        0x20A4
140 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
141 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
142 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
143 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
144 #define _PSB_VSYNC_PIPEB_FLAG	  (1<<5)
145 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
146 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
147 #define _PSB_VSYNC_PIPEA_FLAG	  (1<<7)
148 #define _MDFLD_MIPIA_FLAG	  (1<<16)
149 #define _MDFLD_MIPIC_FLAG	  (1<<17)
150 #define _PSB_IRQ_SGX_FLAG	  (1<<18)
151 #define _PSB_IRQ_MSVDX_FLAG	  (1<<19)
152 #define _LNC_IRQ_TOPAZ_FLAG	  (1<<20)
153 
154 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
155 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | _MDFLD_PIPEB_EVENT_FLAG | \
156         _PSB_PIPEA_EVENT_FLAG | _PSB_VSYNC_PIPEA_FLAG | _MDFLD_MIPIA_FLAG | _MDFLD_MIPIC_FLAG)
157 #define PSB_INT_IDENTITY_R	  0x20A4
158 #define PSB_INT_MASK_R		  0x20A8
159 #define PSB_INT_ENABLE_R	  0x20A0
160 
161 #define _PSB_MMU_ER_MASK      0x0001FF00
162 #define _PSB_MMU_ER_HOST      (1 << 16)
163 #define GPIOA			0x5010
164 #define GPIOB			0x5014
165 #define GPIOC			0x5018
166 #define GPIOD			0x501c
167 #define GPIOE			0x5020
168 #define GPIOF			0x5024
169 #define GPIOG			0x5028
170 #define GPIOH			0x502c
171 #define GPIO_CLOCK_DIR_MASK		(1 << 0)
172 #define GPIO_CLOCK_DIR_IN		(0 << 1)
173 #define GPIO_CLOCK_DIR_OUT		(1 << 1)
174 #define GPIO_CLOCK_VAL_MASK		(1 << 2)
175 #define GPIO_CLOCK_VAL_OUT		(1 << 3)
176 #define GPIO_CLOCK_VAL_IN		(1 << 4)
177 #define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
178 #define GPIO_DATA_DIR_MASK		(1 << 8)
179 #define GPIO_DATA_DIR_IN		(0 << 9)
180 #define GPIO_DATA_DIR_OUT		(1 << 9)
181 #define GPIO_DATA_VAL_MASK		(1 << 10)
182 #define GPIO_DATA_VAL_OUT		(1 << 11)
183 #define GPIO_DATA_VAL_IN		(1 << 12)
184 #define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
185 
186 #define VCLK_DIVISOR_VGA0   0x6000
187 #define VCLK_DIVISOR_VGA1   0x6004
188 #define VCLK_POST_DIV	    0x6010
189 
190 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
191 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
192 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
193 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
194 #define PSB_COMM_USER_IRQ (1024 >> 2)
195 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
196 #define PSB_COMM_FW (2048 >> 2)
197 
198 #define PSB_UIRQ_VISTEST	       1
199 #define PSB_UIRQ_OOM_REPLY	       2
200 #define PSB_UIRQ_FIRE_TA_REPLY	       3
201 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
202 
203 #define PSB_2D_SIZE (256*1024*1024)
204 #define PSB_MAX_RELOC_PAGES 1024
205 
206 #define PSB_LOW_REG_OFFS 0x0204
207 #define PSB_HIGH_REG_OFFS 0x0600
208 
209 #define PSB_NUM_VBLANKS 2
210 
211 
212 #define PSB_2D_SIZE (256*1024*1024)
213 #define PSB_MAX_RELOC_PAGES 1024
214 
215 #define PSB_LOW_REG_OFFS 0x0204
216 #define PSB_HIGH_REG_OFFS 0x0600
217 
218 #define PSB_NUM_VBLANKS 2
219 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
220 #define PSB_LID_DELAY (DRM_HZ / 10)
221 
222 #define MDFLD_PNW_A0 0x00
223 #define MDFLD_PNW_B0 0x04
224 #define MDFLD_PNW_C0 0x08
225 
226 #define MDFLD_DSR_2D_3D_0 BIT0
227 #define MDFLD_DSR_2D_3D_2 BIT1
228 #define MDFLD_DSR_CURSOR_0 BIT2
229 #define MDFLD_DSR_CURSOR_2 BIT3
230 #define MDFLD_DSR_OVERLAY_0 BIT4
231 #define MDFLD_DSR_OVERLAY_2 BIT5
232 #define MDFLD_DSR_MIPI_CONTROL	BIT6
233 #define MDFLD_DSR_2D_3D 	(MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
234 
235 #define MDFLD_DSR_RR 45
236 #define MDFLD_DPU_ENABLE BIT31
237 #define MDFLD_DSR_FULLSCREEN BIT30
238 #define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
239 
240 #define PSB_PWR_STATE_ON		1
241 #define PSB_PWR_STATE_OFF		2
242 
243 #define PSB_PMPOLICY_NOPM		0
244 #define PSB_PMPOLICY_CLOCKGATING	1
245 #define PSB_PMPOLICY_POWERDOWN		2
246 
247 #define PSB_PMSTATE_POWERUP		0
248 #define PSB_PMSTATE_CLOCKGATED		1
249 #define PSB_PMSTATE_POWERDOWN		2
250 #define PSB_PCIx_MSI_ADDR_LOC		0x94
251 #define PSB_PCIx_MSI_DATA_LOC		0x98
252 
253 #define MDFLD_PLANE_MAX_WIDTH		2048
254 #define MDFLD_PLANE_MAX_HEIGHT		2048
255 
256 struct opregion_header;
257 struct opregion_acpi;
258 struct opregion_swsci;
259 struct opregion_asle;
260 
261 struct psb_intel_opregion {
262 	struct opregion_header *header;
263 	struct opregion_acpi *acpi;
264 	struct opregion_swsci *swsci;
265 	struct opregion_asle *asle;
266 	int enabled;
267 };
268 
269 /*
270  *User options.
271  */
272 
273 struct drm_psb_uopt {
274 	int pad; /*keep it here in case we use it in future*/
275 };
276 
277 /**
278  *struct psb_context
279  *
280  *@buffers:	 array of pre-allocated validate buffers.
281  *@used_buffers: number of buffers in @buffers array currently in use.
282  *@validate_buffer: buffers validated from user-space.
283  *@kern_validate_buffers : buffers validated from kernel-space.
284  *@fence_flags : Fence flags to be used for fence creation.
285  *
286  *This structure is used during execbuf validation.
287  */
288 
289 struct psb_context {
290 	struct psb_validate_buffer *buffers;
291 	uint32_t used_buffers;
292 	struct list_head validate_list;
293 	struct list_head kern_validate_list;
294 	uint32_t fence_types;
295 	uint32_t val_seq;
296 };
297 
298 struct psb_validate_buffer;
299 
300 /* Currently defined profiles */
301 enum VAProfile {
302 	VAProfileMPEG2Simple		= 0,
303 	VAProfileMPEG2Main		= 1,
304 	VAProfileMPEG4Simple		= 2,
305 	VAProfileMPEG4AdvancedSimple	= 3,
306 	VAProfileMPEG4Main		= 4,
307 	VAProfileH264Baseline		= 5,
308 	VAProfileH264Main		= 6,
309 	VAProfileH264High		= 7,
310 	VAProfileVC1Simple		= 8,
311 	VAProfileVC1Main		= 9,
312 	VAProfileVC1Advanced		= 10,
313 	VAProfileH263Baseline		= 11,
314 	VAProfileJPEGBaseline           = 12,
315 	VAProfileH264ConstrainedBaseline = 13
316 };
317 
318 /* Currently defined entrypoints */
319 enum VAEntrypoint {
320 	VAEntrypointVLD		= 1,
321 	VAEntrypointIZZ		= 2,
322 	VAEntrypointIDCT	= 3,
323 	VAEntrypointMoComp	= 4,
324 	VAEntrypointDeblocking	= 5,
325 	VAEntrypointEncSlice	= 6,	/* slice level encode */
326 	VAEntrypointEncPicture 	= 7	/* pictuer encode, JPEG, etc */
327 };
328 
329 
330 struct psb_video_ctx {
331 	struct list_head head;
332 	struct file *filp; /* DRM device file pointer */
333 	int ctx_type; /* profile<<8|entrypoint */
334 	/* todo: more context specific data for multi-context support */
335 };
336 
337 #define MODE_SETTING_IN_CRTC 	0x1
338 #define MODE_SETTING_IN_ENCODER 0x2
339 #define MODE_SETTING_ON_GOING 	0x3
340 #define MODE_SETTING_IN_DSR 	0x4
341 #define MODE_SETTING_ENCODER_DONE 0x8
342 #define GCT_R10_HEADER_SIZE	16
343 #define GCT_R10_DISPLAY_DESC_SIZE	28
344 
345 struct drm_psb_private {
346 	/*
347 	 * DSI info.
348 	 */
349 	void * dbi_dsr_info;
350 	void * dsi_configs[2];
351 
352 	/*
353 	 *TTM Glue.
354 	 */
355 
356 	struct drm_global_reference mem_global_ref;
357 	struct ttm_bo_global_ref bo_global_ref;
358 	int has_global;
359 
360 	struct drm_device *dev;
361 	struct ttm_object_device *tdev;
362 	struct ttm_fence_device fdev;
363 	struct ttm_bo_device bdev;
364 	struct ttm_lock ttm_lock;
365 	struct vm_operations_struct *ttm_vm_ops;
366 	int has_fence_device;
367 	int has_bo_device;
368 
369 	unsigned long chipset;
370 
371 	struct drm_psb_uopt uopt;
372 
373 	struct psb_gtt *pg;
374 
375 	/*GTT Memory manager*/
376 	struct psb_gtt_mm *gtt_mm;
377 
378 	struct page *scratch_page;
379 	uint32_t sequence[PSB_NUM_ENGINES];
380 	uint32_t last_sequence[PSB_NUM_ENGINES];
381 	uint32_t last_submitted_seq[PSB_NUM_ENGINES];
382 
383 	struct psb_mmu_driver *mmu;
384 	struct psb_mmu_pd *pf_pd;
385 
386 	uint8_t *sgx_reg;
387 	uint8_t *vdc_reg;
388 	uint32_t gatt_free_offset;
389 
390 	/* IMG video context */
391 	struct list_head video_ctx;
392 
393 
394 
395 	/*
396 	 *Fencing / irq.
397 	 */
398 
399 	uint32_t vdc_irq_mask;
400 	uint32_t pipestat[PSB_NUM_PIPE];
401 	bool vblanksEnabledForFlips;
402 
403 	spinlock_t irqmask_lock;
404 	spinlock_t sequence_lock;
405 
406 	/*
407 	 *Modesetting
408 	 */
409 	struct psb_intel_mode_device mode_dev;
410 
411 	struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
412 	struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
413 	uint32_t num_pipe;
414 
415 	/*
416 	 * CI share buffer
417 	 */
418 	unsigned int ci_region_start;
419 	unsigned int ci_region_size;
420 
421 	/*
422 	 * RAR share buffer;
423 	 */
424 	unsigned int rar_region_start;
425 	unsigned int rar_region_size;
426 
427 	/*
428 	 *Memory managers
429 	 */
430 
431 	int have_camera;
432 	int have_rar;
433 	int have_tt;
434 	int have_mem_mmu;
435 	struct mutex temp_mem;
436 
437 	/*
438 	 *Relocation buffer mapping.
439 	 */
440 
441 	spinlock_t reloc_lock;
442 	unsigned int rel_mapped_pages;
443 	wait_queue_head_t rel_mapped_queue;
444 
445 	/*
446 	 *SAREA
447 	 */
448 	struct drm_psb_sarea *sarea_priv;
449 
450 	/*
451 	*OSPM info
452 	*/
453 	uint32_t ospm_base;
454 
455 	/*
456 	 * Sizes info
457 	 */
458 
459 	struct drm_psb_sizes_arg sizes;
460 
461 	uint32_t fuse_reg_value;
462 
463 	/* pci revision id for B0:D2:F0 */
464 	uint8_t platform_rev_id;
465 
466 	/*
467 	 *LVDS info
468 	 */
469 	int backlight_duty_cycle;	/* restore backlight to this value */
470 	bool panel_wants_dither;
471 	struct drm_display_mode *panel_fixed_mode;
472 	struct drm_display_mode *lfp_lvds_vbt_mode;
473 	struct drm_display_mode *sdvo_lvds_vbt_mode;
474 
475 	struct bdb_lvds_backlight *lvds_bl; /*LVDS backlight info from VBT*/
476 	struct psb_intel_i2c_chan *lvds_i2c_bus;
477 
478 	/* Feature bits from the VBIOS*/
479 	unsigned int int_tv_support:1;
480 	unsigned int lvds_dither:1;
481 	unsigned int lvds_vbt:1;
482 	unsigned int int_crt_support:1;
483 	unsigned int lvds_use_ssc:1;
484 	int lvds_ssc_freq;
485 	bool is_lvds_on;
486 
487 	unsigned int core_freq;
488 	uint32_t iLVDS_enable;
489 
490 	/*runtime PM state*/
491 	int rpm_enabled;
492 
493 	/*
494 	 *Register state
495 	 */
496 	uint32_t saveDSPACNTR;
497 	uint32_t saveDSPBCNTR;
498 	uint32_t savePIPEACONF;
499 	uint32_t savePIPEBCONF;
500 	uint32_t savePIPEASRC;
501 	uint32_t savePIPEBSRC;
502 	uint32_t saveFPA0;
503 	uint32_t saveFPA1;
504 	uint32_t saveDPLL_A;
505 	uint32_t saveDPLL_A_MD;
506 	uint32_t saveHTOTAL_A;
507 	uint32_t saveHBLANK_A;
508 	uint32_t saveHSYNC_A;
509 	uint32_t saveVTOTAL_A;
510 	uint32_t saveVBLANK_A;
511 	uint32_t saveVSYNC_A;
512 	uint32_t saveDSPASTRIDE;
513 	uint32_t saveDSPASIZE;
514 	uint32_t saveDSPAPOS;
515 	uint32_t saveDSPABASE;
516 	uint32_t saveDSPASURF;
517 	uint32_t saveFPB0;
518 	uint32_t saveFPB1;
519 	uint32_t saveDPLL_B;
520 	uint32_t saveDPLL_B_MD;
521 	uint32_t saveHTOTAL_B;
522 	uint32_t saveHBLANK_B;
523 	uint32_t saveHSYNC_B;
524 	uint32_t saveVTOTAL_B;
525 	uint32_t saveVBLANK_B;
526 	uint32_t saveVSYNC_B;
527 	uint32_t saveDSPBSTRIDE;
528 	uint32_t saveDSPBSIZE;
529 	uint32_t saveDSPBPOS;
530 	uint32_t saveDSPBBASE;
531 	uint32_t saveDSPBSURF;
532 	uint32_t saveVCLK_DIVISOR_VGA0;
533 	uint32_t saveVCLK_DIVISOR_VGA1;
534 	uint32_t saveVCLK_POST_DIV;
535 	uint32_t saveVGACNTRL;
536 	uint32_t saveADPA;
537 	uint32_t saveLVDS;
538 	uint32_t saveDVOA;
539 	uint32_t saveDVOB;
540 	uint32_t saveDVOC;
541 	uint32_t savePP_ON;
542 	uint32_t savePP_OFF;
543 	uint32_t savePP_CONTROL;
544 	uint32_t savePP_CYCLE;
545 	uint32_t savePFIT_CONTROL;
546 	uint32_t savePaletteA[256];
547 	uint32_t savePaletteB[256];
548 	uint32_t saveBLC_PWM_CTL2;
549 	uint32_t saveBLC_PWM_CTL;
550 	uint32_t saveCLOCKGATING;
551 	uint32_t saveDSPARB;
552 	uint32_t saveDSPATILEOFF;
553 	uint32_t saveDSPBTILEOFF;
554 	uint32_t saveDSPAADDR;
555 	uint32_t saveDSPBADDR;
556 	uint32_t savePFIT_AUTO_RATIOS;
557 	uint32_t savePFIT_PGM_RATIOS;
558 	uint32_t savePP_ON_DELAYS;
559 	uint32_t savePP_OFF_DELAYS;
560 	uint32_t savePP_DIVISOR;
561 	uint32_t saveBSM;
562 	uint32_t saveVBT;
563 	uint32_t saveBCLRPAT_A;
564 	uint32_t saveBCLRPAT_B;
565 	uint32_t saveDSPALINOFF;
566 	uint32_t saveDSPBLINOFF;
567 	uint32_t savePERF_MODE;
568 	uint32_t saveDSPFW1;
569 	uint32_t saveDSPFW2;
570 	uint32_t saveDSPFW3;
571 	uint32_t saveDSPFW4;
572 	uint32_t saveDSPFW5;
573 	uint32_t saveDSPFW6;
574 	uint32_t saveCHICKENBIT;
575 	uint32_t saveDSPACURSOR_CTRL;
576 	uint32_t saveDSPBCURSOR_CTRL;
577 	uint32_t saveDSPACURSOR_BASE;
578 	uint32_t saveDSPBCURSOR_BASE;
579 	uint32_t saveDSPACURSOR_POS;
580 	uint32_t saveDSPBCURSOR_POS;
581 	uint32_t save_palette_a[256];
582 	uint32_t save_palette_b[256];
583 	uint32_t saveOV_OVADD;
584 	uint32_t saveOV_OGAMC0;
585 	uint32_t saveOV_OGAMC1;
586 	uint32_t saveOV_OGAMC2;
587 	uint32_t saveOV_OGAMC3;
588 	uint32_t saveOV_OGAMC4;
589 	uint32_t saveOV_OGAMC5;
590 	uint32_t saveOVC_OVADD;
591 	uint32_t saveOVC_OGAMC0;
592 	uint32_t saveOVC_OGAMC1;
593 	uint32_t saveOVC_OGAMC2;
594 	uint32_t saveOVC_OGAMC3;
595 	uint32_t saveOVC_OGAMC4;
596 	uint32_t saveOVC_OGAMC5;
597 
598 	/*
599 	 * extra MDFLD Register state
600 	 */
601 	uint32_t saveHDMIPHYMISCCTL;
602 	uint32_t saveHDMIB_CONTROL;
603 	uint32_t saveDSPCCNTR;
604 	uint32_t savePIPECCONF;
605 	uint32_t savePIPECSRC;
606 	uint32_t saveHTOTAL_C;
607 	uint32_t saveHBLANK_C;
608 	uint32_t saveHSYNC_C;
609 	uint32_t saveVTOTAL_C;
610 	uint32_t saveVBLANK_C;
611 	uint32_t saveVSYNC_C;
612 	uint32_t saveDSPCSTRIDE;
613 	uint32_t saveDSPCSIZE;
614 	uint32_t saveDSPCPOS;
615 	uint32_t saveDSPCSURF;
616 	uint32_t saveDSPCLINOFF;
617 	uint32_t saveDSPCTILEOFF;
618 	uint32_t saveDSPCCURSOR_CTRL;
619 	uint32_t saveDSPCCURSOR_BASE;
620 	uint32_t saveDSPCCURSOR_POS;
621 	uint32_t save_palette_c[256];
622 	uint32_t saveOV_OVADD_C;
623 	uint32_t saveOV_OGAMC0_C;
624 	uint32_t saveOV_OGAMC1_C;
625 	uint32_t saveOV_OGAMC2_C;
626 	uint32_t saveOV_OGAMC3_C;
627 	uint32_t saveOV_OGAMC4_C;
628 	uint32_t saveOV_OGAMC5_C;
629 
630 	/* DSI reg save */
631 	uint32_t saveDEVICE_READY_REG;
632 	uint32_t saveINTR_EN_REG;
633 	uint32_t saveDSI_FUNC_PRG_REG;
634 	uint32_t saveHS_TX_TIMEOUT_REG;
635 	uint32_t saveLP_RX_TIMEOUT_REG;
636 	uint32_t saveTURN_AROUND_TIMEOUT_REG;
637 	uint32_t saveDEVICE_RESET_REG;
638 	uint32_t saveDPI_RESOLUTION_REG;
639 	uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
640 	uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
641 	uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
642 	uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
643 	uint32_t saveVERT_SYNC_PAD_COUNT_REG;
644 	uint32_t saveVERT_BACK_PORCH_COUNT_REG;
645 	uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
646 	uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
647 	uint32_t saveINIT_COUNT_REG;
648 	uint32_t saveMAX_RET_PAK_REG;
649 	uint32_t saveVIDEO_FMT_REG;
650 	uint32_t saveEOT_DISABLE_REG;
651 	uint32_t saveLP_BYTECLK_REG;
652 	uint32_t saveHS_LS_DBI_ENABLE_REG;
653 	uint32_t saveTXCLKESC_REG;
654 	uint32_t saveDPHY_PARAM_REG;
655 	uint32_t saveMIPI_CONTROL_REG;
656 	uint32_t saveMIPI;
657 	uint32_t saveMIPI_C;
658 	void (*init_drvIC)(struct drm_device *dev);
659 	void (*dsi_prePowerState)(struct drm_device *dev);
660 	void (*dsi_postPowerState)(struct drm_device *dev);
661 
662 	/* DPST Register Save */
663 	uint32_t saveHISTOGRAM_INT_CONTROL_REG;
664 	uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
665 	uint32_t savePWM_CONTROL_LOGIC;
666 
667 	/* MSI reg save */
668 
669 	uint32_t msi_addr;
670 	uint32_t msi_data;
671 
672 	/*
673 	 *Scheduling.
674 	 */
675 
676 	struct mutex reset_mutex;
677 	struct mutex cmdbuf_mutex;
678 	/*uint32_t ta_mem_pages;
679 	struct psb_ta_mem *ta_mem;
680 	int force_ta_mem_load;*/
681 	atomic_t val_seq;
682 
683 	/*
684 	 *TODO: change this to be per drm-context.
685 	 */
686 
687 	struct psb_context context;
688 
689 	/*
690 	 * LID-Switch
691 	 */
692 	spinlock_t lid_lock;
693 	struct timer_list lid_timer;
694 	struct psb_intel_opregion opregion;
695 	u32 *lid_state;
696 	u32 lid_last_state;
697 
698 	/*
699 	 *Watchdog
700 	 */
701 
702 	int timer_available;
703 
704 	uint32_t apm_reg;
705 	uint16_t apm_base;
706 
707 	/*
708 	 * Used for modifying backlight from
709 	 * xrandr -- consider removing and using HAL instead
710 	 */
711 	struct drm_property *backlight_property;
712 	uint32_t blc_adj1;
713 	uint32_t blc_adj2;
714 
715 	void * fbdev;
716 };
717 
718 
719 struct psb_file_data {	/* TODO: Audit this, remove the indirection and set
720 			   it up properly in open/postclose  ACFIXME */
721 	void *priv;
722 };
723 
724 struct psb_fpriv {
725 	struct ttm_object_file *tfile;
726 };
727 
728 struct psb_mmu_driver;
729 
730 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
731 extern int drm_pick_crtcs(struct drm_device *dev);
732 
psb_fpriv(struct drm_file * file_priv)733 static inline struct psb_fpriv *psb_fpriv(struct drm_file *file_priv)
734 {
735 	struct psb_file_data *pvr_file_priv
736 			= (struct psb_file_data *)file_priv->driver_priv;
737 	return (struct psb_fpriv *) pvr_file_priv->priv;
738 }
739 
psb_priv(struct drm_device * dev)740 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
741 {
742 	return (struct drm_psb_private *) dev->dev_private;
743 }
744 
745 /*
746  *TTM glue. psb_ttm_glue.c
747  */
748 
749 extern int psb_open(struct inode *inode, struct file *filp);
750 extern int psb_release(struct inode *inode, struct file *filp);
751 extern int psb_mmap(struct file *filp, struct vm_area_struct *vma);
752 
753 extern int psb_fence_signaled_ioctl(struct drm_device *dev, void *data,
754 				    struct drm_file *file_priv);
755 extern int psb_verify_access(struct ttm_buffer_object *bo,
756 			     struct file *filp);
757 extern ssize_t psb_ttm_read(struct file *filp, char __user *buf,
758 			    size_t count, loff_t *f_pos);
759 extern ssize_t psb_ttm_write(struct file *filp, const char __user *buf,
760 			    size_t count, loff_t *f_pos);
761 extern int psb_fence_finish_ioctl(struct drm_device *dev, void *data,
762 				  struct drm_file *file_priv);
763 extern int psb_fence_unref_ioctl(struct drm_device *dev, void *data,
764 				 struct drm_file *file_priv);
765 extern int psb_pl_waitidle_ioctl(struct drm_device *dev, void *data,
766 				 struct drm_file *file_priv);
767 extern int psb_pl_setstatus_ioctl(struct drm_device *dev, void *data,
768 				  struct drm_file *file_priv);
769 extern int psb_pl_synccpu_ioctl(struct drm_device *dev, void *data,
770 				struct drm_file *file_priv);
771 extern int psb_pl_unref_ioctl(struct drm_device *dev, void *data,
772 			      struct drm_file *file_priv);
773 extern int psb_pl_reference_ioctl(struct drm_device *dev, void *data,
774 				  struct drm_file *file_priv);
775 extern int psb_pl_create_ioctl(struct drm_device *dev, void *data,
776 			       struct drm_file *file_priv);
777 extern int psb_pl_ub_create_ioctl(struct drm_device *dev, void *data,
778 			       struct drm_file *file_priv);
779 extern int psb_extension_ioctl(struct drm_device *dev, void *data,
780 			       struct drm_file *file_priv);
781 extern int psb_ttm_global_init(struct drm_psb_private *dev_priv);
782 extern void psb_ttm_global_release(struct drm_psb_private *dev_priv);
783 extern int psb_getpageaddrs_ioctl(struct drm_device *dev, void *data,
784 				struct drm_file *file_priv);
785 /*
786  *MMU stuff.
787  */
788 
789 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
790 					int trap_pagefaults,
791 					int invalid_type,
792 					struct drm_psb_private *dev_priv);
793 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
794 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
795 						 *driver);
796 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
797 			       uint32_t gtt_start, uint32_t gtt_pages);
798 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
799 					   int trap_pagefaults,
800 					   int invalid_type);
801 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
802 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
803 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
804 					unsigned long address,
805 					uint32_t num_pages);
806 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
807 				       uint32_t start_pfn,
808 				       unsigned long address,
809 				       uint32_t num_pages, int type);
810 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
811 				  unsigned long *pfn);
812 
813 /*
814  *Enable / disable MMU for different requestors.
815  */
816 
817 
818 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
819 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
820 				unsigned long address, uint32_t num_pages,
821 				uint32_t desired_tile_stride,
822 				uint32_t hw_tile_stride, int type);
823 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
824 				 unsigned long address, uint32_t num_pages,
825 				 uint32_t desired_tile_stride,
826 				 uint32_t hw_tile_stride);
827 /*
828  *psb_sgx.c
829  */
830 
831 
832 
833 extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
834 			    struct drm_file *file_priv);
835 extern int psb_reg_submit(struct drm_psb_private *dev_priv,
836 			  uint32_t *regs, unsigned int cmds);
837 
838 
839 extern void psb_fence_or_sync(struct drm_file *file_priv,
840 			      uint32_t engine,
841 			      uint32_t fence_types,
842 			      uint32_t fence_flags,
843 			      struct list_head *list,
844 			      struct psb_ttm_fence_rep *fence_arg,
845 			      struct ttm_fence_object **fence_p);
846 extern int psb_validate_kernel_buffer(struct psb_context *context,
847 				      struct ttm_buffer_object *bo,
848 				      uint32_t fence_class,
849 				      uint64_t set_flags,
850 				      uint64_t clr_flags);
851 
852 /*
853  *psb_irq.c
854  */
855 
856 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
857 extern int psb_irq_enable_dpst(struct drm_device *dev);
858 extern int psb_irq_disable_dpst(struct drm_device *dev);
859 extern void psb_irq_preinstall(struct drm_device *dev);
860 extern int psb_irq_postinstall(struct drm_device *dev);
861 extern void psb_irq_uninstall(struct drm_device *dev);
862 extern void psb_irq_preinstall_islands(struct drm_device *dev, int hw_islands);
863 extern int psb_irq_postinstall_islands(struct drm_device *dev, int hw_islands);
864 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
865 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
866 
867 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
868 extern int psb_vblank_wait2(struct drm_device *dev,unsigned int *sequence);
869 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
870 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
871 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
872 void
873 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
874 
875 void
876 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
877 
878 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
879 
880 /*
881  *psb_fence.c
882  */
883 
884 extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
885 
886 extern int psb_fence_emit_sequence(struct ttm_fence_device *fdev,
887 				   uint32_t fence_class,
888 				   uint32_t flags, uint32_t *sequence,
889 				   unsigned long *timeout_jiffies);
890 extern void psb_fence_error(struct drm_device *dev,
891 			    uint32_t class,
892 			    uint32_t sequence, uint32_t type, int error);
893 extern int psb_ttm_fence_device_init(struct ttm_fence_device *fdev);
894 
895 /* MSVDX/Topaz stuff */
896 extern int psb_remove_videoctx(struct drm_psb_private *dev_priv, struct file *filp);
897 
898 extern int lnc_video_frameskip(struct drm_device *dev,
899 			       uint64_t user_pointer);
900 extern int lnc_video_getparam(struct drm_device *dev, void *data,
901 			      struct drm_file *file_priv);
902 
903 /*
904  * psb_opregion.c
905  */
906 extern int psb_intel_opregion_init(struct drm_device *dev);
907 
908 /*
909  *psb_fb.c
910  */
911 extern int psbfb_probed(struct drm_device *dev);
912 extern int psbfb_remove(struct drm_device *dev,
913 			struct drm_framebuffer *fb);
914 extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
915 			       struct drm_file *file_priv);
916 extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
917 			      struct drm_file *file_priv);
918 extern void *psbfb_vdc_reg(struct drm_device* dev);
919 
920 /*
921  * psb_2d.c
922  */
923 extern void psbfb_fillrect(struct fb_info *info,
924 					const struct fb_fillrect *rect);
925 extern void psbfb_copyarea(struct fb_info *info,
926 					const struct fb_copyarea *region);
927 extern void psbfb_imageblit(struct fb_info *info,
928 					const struct fb_image *image);
929 extern int psbfb_sync(struct fb_info *info);
930 
931 extern void psb_spank(struct drm_psb_private *dev_priv);
932 
933 /*
934  *psb_reset.c
935  */
936 
937 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
938 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
939 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
940 
941 /* modesetting */
942 extern void psb_modeset_init(struct drm_device *dev);
943 extern void psb_modeset_cleanup(struct drm_device *dev);
944 extern int psb_fbdev_init(struct drm_device * dev);
945 
946 /* psb_bl.c */
947 int psb_backlight_init(struct drm_device *dev);
948 void psb_backlight_exit(void);
949 int psb_set_brightness(struct backlight_device *bd);
950 int psb_get_brightness(struct backlight_device *bd);
951 struct backlight_device * psb_get_backlight_device(void);
952 
953 /*
954  *Debug print bits setting
955  */
956 #define PSB_D_GENERAL (1 << 0)
957 #define PSB_D_INIT    (1 << 1)
958 #define PSB_D_IRQ     (1 << 2)
959 #define PSB_D_ENTRY   (1 << 3)
960 /* debug the get H/V BP/FP count */
961 #define PSB_D_HV      (1 << 4)
962 #define PSB_D_DBI_BF  (1 << 5)
963 #define PSB_D_PM      (1 << 6)
964 #define PSB_D_RENDER  (1 << 7)
965 #define PSB_D_REG     (1 << 8)
966 #define PSB_D_MSVDX   (1 << 9)
967 #define PSB_D_TOPAZ   (1 << 10)
968 
969 #ifndef DRM_DEBUG_CODE
970 /* To enable debug printout, set drm_psb_debug in psb_drv.c
971  * to any combination of above print flags.
972  */
973 /* #define DRM_DEBUG_CODE 2 */
974 #endif
975 
976 extern int drm_psb_debug;
977 extern int drm_psb_no_fb;
978 extern int drm_psb_disable_vsync;
979 extern int drm_idle_check_interval;
980 
981 #define PSB_DEBUG_GENERAL(_fmt, _arg...) \
982 	PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
983 #define PSB_DEBUG_INIT(_fmt, _arg...) \
984 	PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
985 #define PSB_DEBUG_IRQ(_fmt, _arg...) \
986 	PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
987 #define PSB_DEBUG_ENTRY(_fmt, _arg...) \
988 	PSB_DEBUG(PSB_D_ENTRY, _fmt, ##_arg)
989 #define PSB_DEBUG_HV(_fmt, _arg...) \
990 	PSB_DEBUG(PSB_D_HV, _fmt, ##_arg)
991 #define PSB_DEBUG_DBI_BF(_fmt, _arg...) \
992 	PSB_DEBUG(PSB_D_DBI_BF, _fmt, ##_arg)
993 #define PSB_DEBUG_PM(_fmt, _arg...) \
994 	PSB_DEBUG(PSB_D_PM, _fmt, ##_arg)
995 #define PSB_DEBUG_RENDER(_fmt, _arg...) \
996 	PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
997 #define PSB_DEBUG_REG(_fmt, _arg...) \
998 	PSB_DEBUG(PSB_D_REG, _fmt, ##_arg)
999 #define PSB_DEBUG_MSVDX(_fmt, _arg...) \
1000 	PSB_DEBUG(PSB_D_MSVDX, _fmt, ##_arg)
1001 #define PSB_DEBUG_TOPAZ(_fmt, _arg...) \
1002 	PSB_DEBUG(PSB_D_TOPAZ, _fmt, ##_arg)
1003 
1004 #if DRM_DEBUG_CODE
1005 #define PSB_DEBUG(_flag, _fmt, _arg...)					\
1006 	do {								\
1007 		if (unlikely((_flag) & drm_psb_debug))			\
1008 			printk(KERN_DEBUG				\
1009 			       "[psb:0x%02x:%s] " _fmt , _flag,		\
1010 			       __func__ , ##_arg);			\
1011 	} while (0)
1012 #else
1013 #define PSB_DEBUG(_fmt, _arg...)     do { } while (0)
1014 #endif
1015 
1016 /*
1017  *Utilities
1018  */
1019 #define DRM_DRIVER_PRIVATE_T struct drm_psb_private
1020 
MRST_MSG_READ32(uint port,uint offset)1021 static inline u32 MRST_MSG_READ32(uint port, uint offset)
1022 {
1023 	int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
1024 	uint32_t ret_val = 0;
1025 	struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1026 	pci_write_config_dword (pci_root, 0xD0, mcr);
1027 	pci_read_config_dword (pci_root, 0xD4, &ret_val);
1028 	pci_dev_put(pci_root);
1029 	return ret_val;
1030 }
MRST_MSG_WRITE32(uint port,uint offset,u32 value)1031 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
1032 {
1033 	int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
1034 	struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1035 	pci_write_config_dword (pci_root, 0xD4, value);
1036 	pci_write_config_dword (pci_root, 0xD0, mcr);
1037 	pci_dev_put(pci_root);
1038 }
MDFLD_MSG_READ32(uint port,uint offset)1039 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
1040 {
1041 	int mcr = (0x10<<24) | (port << 16) | (offset << 8);
1042 	uint32_t ret_val = 0;
1043 	struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1044 	pci_write_config_dword (pci_root, 0xD0, mcr);
1045 	pci_read_config_dword (pci_root, 0xD4, &ret_val);
1046 	pci_dev_put(pci_root);
1047 	return ret_val;
1048 }
MDFLD_MSG_WRITE32(uint port,uint offset,u32 value)1049 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
1050 {
1051 	int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
1052 	struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1053 	pci_write_config_dword (pci_root, 0xD4, value);
1054 	pci_write_config_dword (pci_root, 0xD0, mcr);
1055 	pci_dev_put(pci_root);
1056 }
1057 
REGISTER_READ(struct drm_device * dev,uint32_t reg)1058 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
1059 {
1060 	struct drm_psb_private *dev_priv = dev->dev_private;
1061 	int reg_val = ioread32(dev_priv->vdc_reg + (reg));
1062 	PSB_DEBUG_REG("reg = 0x%x. reg_val = 0x%x. \n", reg, reg_val);
1063 	return reg_val;
1064 }
1065 
1066 #define REG_READ(reg)	       REGISTER_READ(dev, (reg))
REGISTER_WRITE(struct drm_device * dev,uint32_t reg,uint32_t val)1067 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
1068 				      uint32_t val)
1069 {
1070 	struct drm_psb_private *dev_priv = dev->dev_private;
1071 	if ((reg < 0x70084 || reg >0x70088) && (reg < 0xa000 || reg >0xa3ff))
1072 		PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
1073 
1074 	iowrite32((val), dev_priv->vdc_reg + (reg));
1075 }
1076 
1077 #define REG_WRITE(reg, val)	REGISTER_WRITE(dev, (reg), (val))
1078 
REGISTER_WRITE16(struct drm_device * dev,uint32_t reg,uint32_t val)1079 static inline void REGISTER_WRITE16(struct drm_device *dev,
1080 					uint32_t reg, uint32_t val)
1081 {
1082 	struct drm_psb_private *dev_priv = dev->dev_private;
1083 
1084 	PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
1085 
1086 	iowrite16((val), dev_priv->vdc_reg + (reg));
1087 }
1088 
1089 #define REG_WRITE16(reg, val)	  REGISTER_WRITE16(dev, (reg), (val))
1090 
REGISTER_WRITE8(struct drm_device * dev,uint32_t reg,uint32_t val)1091 static inline void REGISTER_WRITE8(struct drm_device *dev,
1092 				       uint32_t reg, uint32_t val)
1093 {
1094 	struct drm_psb_private *dev_priv = dev->dev_private;
1095 
1096 	PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
1097 
1098 	iowrite8((val), dev_priv->vdc_reg + (reg));
1099 }
1100 
1101 #define REG_WRITE8(reg, val)	 REGISTER_WRITE8(dev, (reg), (val))
1102 
1103 #define PSB_ALIGN_TO(_val, _align) \
1104   (((_val) + ((_align) - 1)) & ~((_align) - 1))
1105 #define PSB_WVDC32(_val, _offs) \
1106   iowrite32(_val, dev_priv->vdc_reg + (_offs))
1107 #define PSB_RVDC32(_offs) \
1108   ioread32(dev_priv->vdc_reg + (_offs))
1109 
1110 /* #define TRAP_SGX_PM_FAULT 1 */
1111 #ifdef TRAP_SGX_PM_FAULT
1112 #define PSB_RSGX32(_offs)					\
1113 ({								\
1114     if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) {		\
1115 	printk(KERN_ERR "access sgx when it's off!! (READ) %s, %d\n", \
1116 	       __FILE__, __LINE__);				\
1117 	mdelay(1000);						\
1118     }								\
1119     ioread32(dev_priv->sgx_reg + (_offs));			\
1120 })
1121 #else
1122 #define PSB_RSGX32(_offs)					\
1123   ioread32(dev_priv->sgx_reg + (_offs))
1124 #endif
1125 #define PSB_WSGX32(_val, _offs) \
1126   iowrite32(_val, dev_priv->sgx_reg + (_offs))
1127 
1128 #define MSVDX_REG_DUMP 0
1129 #if MSVDX_REG_DUMP
1130 
1131 #define PSB_WMSVDX32(_val, _offs) \
1132   printk("MSVDX: write %08x to reg 0x%08x\n", (unsigned int)(_val), (unsigned int)(_offs));\
1133   iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1134 #define PSB_RMSVDX32(_offs) \
1135   ioread32(dev_priv->msvdx_reg + (_offs))
1136 
1137 #else
1138 
1139 #define PSB_WMSVDX32(_val, _offs) \
1140   iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1141 #define PSB_RMSVDX32(_offs) \
1142   ioread32(dev_priv->msvdx_reg + (_offs))
1143 
1144 #endif
1145 
1146 #define PSB_ALPL(_val, _base)			\
1147   (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
1148 #define PSB_ALPLM(_val, _base)			\
1149   ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
1150 
1151 #endif
1152