1 /* linux/arch/arm/mach-s3c2416/clock.c
2 *
3 * Copyright (c) 2010 Simtec Electronics
4 * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
5 *
6 * S3C2416 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/clk.h>
16
17 #include <plat/s3c2416.h>
18 #include <plat/s3c2443.h>
19 #include <plat/clock.h>
20 #include <plat/clock-clksrc.h>
21 #include <plat/cpu.h>
22
23 #include <plat/cpu-freq.h>
24 #include <plat/pll6553x.h>
25 #include <plat/pll.h>
26
27 #include <asm/mach/map.h>
28
29 #include <mach/regs-clock.h>
30 #include <mach/regs-s3c2443-clock.h>
31
32 static unsigned int armdiv[8] = {
33 [0] = 1,
34 [1] = 2,
35 [2] = 3,
36 [3] = 4,
37 [5] = 6,
38 [7] = 8,
39 };
40
41 static struct clksrc_clk hsmmc_div[] = {
42 [0] = {
43 .clk = {
44 .name = "hsmmc-div",
45 .id = 0,
46 .parent = &clk_esysclk.clk,
47 },
48 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
49 },
50 [1] = {
51 .clk = {
52 .name = "hsmmc-div",
53 .id = 1,
54 .parent = &clk_esysclk.clk,
55 },
56 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
57 },
58 };
59
60 static struct clksrc_clk hsmmc_mux[] = {
61 [0] = {
62 .clk = {
63 .id = 0,
64 .name = "hsmmc-if",
65 .ctrlbit = (1 << 6),
66 .enable = s3c2443_clkcon_enable_s,
67 },
68 .sources = &(struct clksrc_sources) {
69 .nr_sources = 2,
70 .sources = (struct clk *[]) {
71 [0] = &hsmmc_div[0].clk,
72 [1] = NULL, /* to fix */
73 },
74 },
75 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
76 },
77 [1] = {
78 .clk = {
79 .id = 1,
80 .name = "hsmmc-if",
81 .ctrlbit = (1 << 12),
82 .enable = s3c2443_clkcon_enable_s,
83 },
84 .sources = &(struct clksrc_sources) {
85 .nr_sources = 2,
86 .sources = (struct clk *[]) {
87 [0] = &hsmmc_div[1].clk,
88 [1] = NULL, /* to fix */
89 },
90 },
91 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
92 },
93 };
94
95 static struct clk hsmmc0_clk = {
96 .name = "hsmmc",
97 .id = 0,
98 .parent = &clk_h,
99 .enable = s3c2443_clkcon_enable_h,
100 .ctrlbit = S3C2416_HCLKCON_HSMMC0,
101 };
102
s3c2416_fclk_div(unsigned long clkcon0)103 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
104 {
105 clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
106
107 return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
108 }
109
s3c2416_setup_clocks(void)110 void __init_or_cpufreq s3c2416_setup_clocks(void)
111 {
112 s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
113 }
114
115
116 static struct clksrc_clk *clksrcs[] __initdata = {
117 &hsmmc_div[0],
118 &hsmmc_div[1],
119 &hsmmc_mux[0],
120 &hsmmc_mux[1],
121 };
122
s3c2416_init_clocks(int xtal)123 void __init s3c2416_init_clocks(int xtal)
124 {
125 u32 epllcon = __raw_readl(S3C2443_EPLLCON);
126 u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
127 int ptr;
128
129 /* s3c2416 EPLL compatible with s3c64xx */
130 clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
131
132 clk_epll.parent = &clk_epllref.clk;
133
134 s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
135
136 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
137 s3c_register_clksrc(clksrcs[ptr], 1);
138
139 s3c24xx_register_clock(&hsmmc0_clk);
140
141 s3c_pwmclk_init();
142
143 }
144