1 /* 2 * This file is part of wl1251 3 * 4 * Copyright (c) 1998-2007 Texas Instruments Incorporated 5 * Copyright (C) 2008-2009 Nokia Corporation 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 19 * 02110-1301 USA 20 * 21 */ 22 23 #ifndef __WL1251_H__ 24 #define __WL1251_H__ 25 26 #include <linux/mutex.h> 27 #include <linux/list.h> 28 #include <linux/bitops.h> 29 #include <net/mac80211.h> 30 31 #define DRIVER_NAME "wl1251" 32 #define DRIVER_PREFIX DRIVER_NAME ": " 33 34 enum { 35 DEBUG_NONE = 0, 36 DEBUG_IRQ = BIT(0), 37 DEBUG_SPI = BIT(1), 38 DEBUG_BOOT = BIT(2), 39 DEBUG_MAILBOX = BIT(3), 40 DEBUG_NETLINK = BIT(4), 41 DEBUG_EVENT = BIT(5), 42 DEBUG_TX = BIT(6), 43 DEBUG_RX = BIT(7), 44 DEBUG_SCAN = BIT(8), 45 DEBUG_CRYPT = BIT(9), 46 DEBUG_PSM = BIT(10), 47 DEBUG_MAC80211 = BIT(11), 48 DEBUG_CMD = BIT(12), 49 DEBUG_ACX = BIT(13), 50 DEBUG_ALL = ~0, 51 }; 52 53 #define DEBUG_LEVEL (DEBUG_NONE) 54 55 #define DEBUG_DUMP_LIMIT 1024 56 57 #define wl1251_error(fmt, arg...) \ 58 printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg) 59 60 #define wl1251_warning(fmt, arg...) \ 61 printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg) 62 63 #define wl1251_notice(fmt, arg...) \ 64 printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg) 65 66 #define wl1251_info(fmt, arg...) \ 67 printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg) 68 69 #define wl1251_debug(level, fmt, arg...) \ 70 do { \ 71 if (level & DEBUG_LEVEL) \ 72 printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \ 73 } while (0) 74 75 #define wl1251_dump(level, prefix, buf, len) \ 76 do { \ 77 if (level & DEBUG_LEVEL) \ 78 print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ 79 DUMP_PREFIX_OFFSET, 16, 1, \ 80 buf, \ 81 min_t(size_t, len, DEBUG_DUMP_LIMIT), \ 82 0); \ 83 } while (0) 84 85 #define wl1251_dump_ascii(level, prefix, buf, len) \ 86 do { \ 87 if (level & DEBUG_LEVEL) \ 88 print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ 89 DUMP_PREFIX_OFFSET, 16, 1, \ 90 buf, \ 91 min_t(size_t, len, DEBUG_DUMP_LIMIT), \ 92 true); \ 93 } while (0) 94 95 #define WL1251_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \ 96 CFG_BSSID_FILTER_EN) 97 98 #define WL1251_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN | \ 99 CFG_RX_MGMT_EN | \ 100 CFG_RX_DATA_EN | \ 101 CFG_RX_CTL_EN | \ 102 CFG_RX_BCN_EN | \ 103 CFG_RX_AUTH_EN | \ 104 CFG_RX_ASSOC_EN) 105 106 #define WL1251_BUSY_WORD_LEN 8 107 108 struct boot_attr { 109 u32 radio_type; 110 u8 mac_clock; 111 u8 arm_clock; 112 int firmware_debug; 113 u32 minor; 114 u32 major; 115 u32 bugfix; 116 }; 117 118 enum wl1251_state { 119 WL1251_STATE_OFF, 120 WL1251_STATE_ON, 121 WL1251_STATE_PLT, 122 }; 123 124 enum wl1251_partition_type { 125 PART_DOWN, 126 PART_WORK, 127 PART_DRPW, 128 129 PART_TABLE_LEN 130 }; 131 132 struct wl1251_partition { 133 u32 size; 134 u32 start; 135 }; 136 137 struct wl1251_partition_set { 138 struct wl1251_partition mem; 139 struct wl1251_partition reg; 140 }; 141 142 struct wl1251; 143 144 struct wl1251_stats { 145 struct acx_statistics *fw_stats; 146 unsigned long fw_stats_update; 147 148 unsigned int retry_count; 149 unsigned int excessive_retries; 150 }; 151 152 struct wl1251_debugfs { 153 struct dentry *rootdir; 154 struct dentry *fw_statistics; 155 156 struct dentry *tx_internal_desc_overflow; 157 158 struct dentry *rx_out_of_mem; 159 struct dentry *rx_hdr_overflow; 160 struct dentry *rx_hw_stuck; 161 struct dentry *rx_dropped; 162 struct dentry *rx_fcs_err; 163 struct dentry *rx_xfr_hint_trig; 164 struct dentry *rx_path_reset; 165 struct dentry *rx_reset_counter; 166 167 struct dentry *dma_rx_requested; 168 struct dentry *dma_rx_errors; 169 struct dentry *dma_tx_requested; 170 struct dentry *dma_tx_errors; 171 172 struct dentry *isr_cmd_cmplt; 173 struct dentry *isr_fiqs; 174 struct dentry *isr_rx_headers; 175 struct dentry *isr_rx_mem_overflow; 176 struct dentry *isr_rx_rdys; 177 struct dentry *isr_irqs; 178 struct dentry *isr_tx_procs; 179 struct dentry *isr_decrypt_done; 180 struct dentry *isr_dma0_done; 181 struct dentry *isr_dma1_done; 182 struct dentry *isr_tx_exch_complete; 183 struct dentry *isr_commands; 184 struct dentry *isr_rx_procs; 185 struct dentry *isr_hw_pm_mode_changes; 186 struct dentry *isr_host_acknowledges; 187 struct dentry *isr_pci_pm; 188 struct dentry *isr_wakeups; 189 struct dentry *isr_low_rssi; 190 191 struct dentry *wep_addr_key_count; 192 struct dentry *wep_default_key_count; 193 /* skipping wep.reserved */ 194 struct dentry *wep_key_not_found; 195 struct dentry *wep_decrypt_fail; 196 struct dentry *wep_packets; 197 struct dentry *wep_interrupt; 198 199 struct dentry *pwr_ps_enter; 200 struct dentry *pwr_elp_enter; 201 struct dentry *pwr_missing_bcns; 202 struct dentry *pwr_wake_on_host; 203 struct dentry *pwr_wake_on_timer_exp; 204 struct dentry *pwr_tx_with_ps; 205 struct dentry *pwr_tx_without_ps; 206 struct dentry *pwr_rcvd_beacons; 207 struct dentry *pwr_power_save_off; 208 struct dentry *pwr_enable_ps; 209 struct dentry *pwr_disable_ps; 210 struct dentry *pwr_fix_tsf_ps; 211 /* skipping cont_miss_bcns_spread for now */ 212 struct dentry *pwr_rcvd_awake_beacons; 213 214 struct dentry *mic_rx_pkts; 215 struct dentry *mic_calc_failure; 216 217 struct dentry *aes_encrypt_fail; 218 struct dentry *aes_decrypt_fail; 219 struct dentry *aes_encrypt_packets; 220 struct dentry *aes_decrypt_packets; 221 struct dentry *aes_encrypt_interrupt; 222 struct dentry *aes_decrypt_interrupt; 223 224 struct dentry *event_heart_beat; 225 struct dentry *event_calibration; 226 struct dentry *event_rx_mismatch; 227 struct dentry *event_rx_mem_empty; 228 struct dentry *event_rx_pool; 229 struct dentry *event_oom_late; 230 struct dentry *event_phy_transmit_error; 231 struct dentry *event_tx_stuck; 232 233 struct dentry *ps_pspoll_timeouts; 234 struct dentry *ps_upsd_timeouts; 235 struct dentry *ps_upsd_max_sptime; 236 struct dentry *ps_upsd_max_apturn; 237 struct dentry *ps_pspoll_max_apturn; 238 struct dentry *ps_pspoll_utilization; 239 struct dentry *ps_upsd_utilization; 240 241 struct dentry *rxpipe_rx_prep_beacon_drop; 242 struct dentry *rxpipe_descr_host_int_trig_rx_data; 243 struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data; 244 struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data; 245 struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data; 246 247 struct dentry *tx_queue_len; 248 struct dentry *tx_queue_status; 249 250 struct dentry *retry_count; 251 struct dentry *excessive_retries; 252 }; 253 254 struct wl1251_if_operations { 255 void (*read)(struct wl1251 *wl, int addr, void *buf, size_t len); 256 void (*write)(struct wl1251 *wl, int addr, void *buf, size_t len); 257 void (*read_elp)(struct wl1251 *wl, int addr, u32 *val); 258 void (*write_elp)(struct wl1251 *wl, int addr, u32 val); 259 int (*power)(struct wl1251 *wl, bool enable); 260 void (*reset)(struct wl1251 *wl); 261 void (*enable_irq)(struct wl1251 *wl); 262 void (*disable_irq)(struct wl1251 *wl); 263 }; 264 265 struct wl1251 { 266 struct ieee80211_hw *hw; 267 bool mac80211_registered; 268 269 void *if_priv; 270 const struct wl1251_if_operations *if_ops; 271 272 void (*set_power)(bool enable); 273 int irq; 274 bool use_eeprom; 275 276 spinlock_t wl_lock; 277 278 enum wl1251_state state; 279 struct mutex mutex; 280 281 int physical_mem_addr; 282 int physical_reg_addr; 283 int virtual_mem_addr; 284 int virtual_reg_addr; 285 286 int cmd_box_addr; 287 int event_box_addr; 288 struct boot_attr boot_attr; 289 290 u8 *fw; 291 size_t fw_len; 292 u8 *nvs; 293 size_t nvs_len; 294 295 u8 bssid[ETH_ALEN]; 296 u8 mac_addr[ETH_ALEN]; 297 u8 bss_type; 298 u8 listen_int; 299 int channel; 300 301 void *target_mem_map; 302 struct acx_data_path_params_resp *data_path; 303 304 /* Number of TX packets transferred to the FW, modulo 16 */ 305 u32 data_in_count; 306 307 /* Frames scheduled for transmission, not handled yet */ 308 struct sk_buff_head tx_queue; 309 bool tx_queue_stopped; 310 311 struct work_struct tx_work; 312 struct work_struct filter_work; 313 314 /* Pending TX frames */ 315 struct sk_buff *tx_frames[16]; 316 317 /* 318 * Index pointing to the next TX complete entry 319 * in the cyclic XT complete array we get from 320 * the FW. 321 */ 322 u32 next_tx_complete; 323 324 /* FW Rx counter */ 325 u32 rx_counter; 326 327 /* Rx frames handled */ 328 u32 rx_handled; 329 330 /* Current double buffer */ 331 u32 rx_current_buffer; 332 u32 rx_last_id; 333 334 /* The target interrupt mask */ 335 u32 intr_mask; 336 struct work_struct irq_work; 337 338 /* The mbox event mask */ 339 u32 event_mask; 340 341 /* Mailbox pointers */ 342 u32 mbox_ptr[2]; 343 344 /* Are we currently scanning */ 345 bool scanning; 346 347 /* Default key (for WEP) */ 348 u32 default_key; 349 350 unsigned int tx_mgmt_frm_rate; 351 unsigned int tx_mgmt_frm_mod; 352 353 unsigned int rx_config; 354 unsigned int rx_filter; 355 356 /* is firmware in elp mode */ 357 bool elp; 358 359 struct delayed_work elp_work; 360 361 /* we can be in psm, but not in elp, we have to differentiate */ 362 bool psm; 363 364 /* PSM mode requested */ 365 bool psm_requested; 366 367 u16 beacon_int; 368 u8 dtim_period; 369 370 /* in dBm */ 371 int power_level; 372 373 int rssi_thold; 374 375 struct wl1251_stats stats; 376 struct wl1251_debugfs debugfs; 377 378 u32 buffer_32; 379 u32 buffer_cmd; 380 u8 buffer_busyword[WL1251_BUSY_WORD_LEN]; 381 struct wl1251_rx_descriptor *rx_descriptor; 382 383 struct ieee80211_vif *vif; 384 385 u32 chip_id; 386 char fw_ver[21]; 387 388 /* Most recently reported noise in dBm */ 389 s8 noise; 390 }; 391 392 int wl1251_plt_start(struct wl1251 *wl); 393 int wl1251_plt_stop(struct wl1251 *wl); 394 395 struct ieee80211_hw *wl1251_alloc_hw(void); 396 int wl1251_free_hw(struct wl1251 *wl); 397 int wl1251_init_ieee80211(struct wl1251 *wl); 398 void wl1251_enable_interrupts(struct wl1251 *wl); 399 void wl1251_disable_interrupts(struct wl1251 *wl); 400 401 #define DEFAULT_HW_GEN_MODULATION_TYPE CCK_LONG /* Long Preamble */ 402 #define DEFAULT_HW_GEN_TX_RATE RATE_2MBPS 403 #define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */ 404 405 #define WL1251_DEFAULT_POWER_LEVEL 20 406 407 #define WL1251_TX_QUEUE_LOW_WATERMARK 10 408 #define WL1251_TX_QUEUE_HIGH_WATERMARK 25 409 410 #define WL1251_DEFAULT_BEACON_INT 100 411 #define WL1251_DEFAULT_DTIM_PERIOD 1 412 413 #define WL1251_DEFAULT_CHANNEL 0 414 415 #define WL1251_DEFAULT_BET_CONSECUTIVE 10 416 417 #define CHIP_ID_1251_PG10 (0x7010101) 418 #define CHIP_ID_1251_PG11 (0x7020101) 419 #define CHIP_ID_1251_PG12 (0x7030101) 420 #define CHIP_ID_1271_PG10 (0x4030101) 421 #define CHIP_ID_1271_PG20 (0x4030111) 422 423 #define WL1251_FW_NAME "wl1251-fw.bin" 424 #define WL1251_NVS_NAME "wl1251-nvs.bin" 425 426 #define WL1251_POWER_ON_SLEEP 10 /* in milliseconds */ 427 428 #define WL1251_PART_DOWN_MEM_START 0x0 429 #define WL1251_PART_DOWN_MEM_SIZE 0x16800 430 #define WL1251_PART_DOWN_REG_START REGISTERS_BASE 431 #define WL1251_PART_DOWN_REG_SIZE REGISTERS_DOWN_SIZE 432 433 #define WL1251_PART_WORK_MEM_START 0x28000 434 #define WL1251_PART_WORK_MEM_SIZE 0x14000 435 #define WL1251_PART_WORK_REG_START REGISTERS_BASE 436 #define WL1251_PART_WORK_REG_SIZE REGISTERS_WORK_SIZE 437 438 #define WL1251_DEFAULT_LOW_RSSI_WEIGHT 10 439 #define WL1251_DEFAULT_LOW_RSSI_DEPTH 10 440 441 #endif 442