1 /*
2  * Copyright (c) 2010 Broadcom Corporation
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _wlc_phy_int_h_
18 #define _wlc_phy_int_h_
19 
20 #include <linux/kernel.h>
21 #include <bcmdefs.h>
22 #include <bcmutils.h>
23 
24 #include <bcmsrom_fmt.h>
25 #include <wlc_phy_hal.h>
26 
27 #define PHYHAL_ERROR	0x0001
28 #define PHYHAL_TRACE	0x0002
29 #define PHYHAL_INFORM	0x0004
30 
31 extern u32 phyhal_msg_level;
32 
33 #define PHY_INFORM_ON()		(phyhal_msg_level & PHYHAL_INFORM)
34 #define PHY_THERMAL_ON()	(phyhal_msg_level & PHYHAL_THERMAL)
35 #define PHY_CAL_ON()		(phyhal_msg_level & PHYHAL_CAL)
36 
37 #ifdef BOARD_TYPE
38 #define BOARDTYPE(_type) BOARD_TYPE
39 #else
40 #define BOARDTYPE(_type) _type
41 #endif
42 
43 #define LCNXN_BASEREV		16
44 
45 struct wlc_hw_info;
46 typedef struct phy_info phy_info_t;
47 typedef void (*initfn_t) (phy_info_t *);
48 typedef void (*chansetfn_t) (phy_info_t *, chanspec_t);
49 typedef int (*longtrnfn_t) (phy_info_t *, int);
50 typedef void (*txiqccgetfn_t) (phy_info_t *, u16 *, u16 *);
51 typedef void (*txiqccsetfn_t) (phy_info_t *, u16, u16);
52 typedef u16(*txloccgetfn_t) (phy_info_t *);
53 typedef void (*radioloftgetfn_t) (phy_info_t *, u8 *, u8 *, u8 *,
54 				  u8 *);
55 typedef s32(*rxsigpwrfn_t) (phy_info_t *, s32);
56 typedef void (*detachfn_t) (phy_info_t *);
57 
58 #undef ISNPHY
59 #undef ISLCNPHY
60 #define ISNPHY(pi)	PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
61 #define ISLCNPHY(pi)  	PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
62 
63 #define ISPHY_11N_CAP(pi)	(ISNPHY(pi) || ISLCNPHY(pi))
64 
65 #define IS20MHZ(pi)	((pi)->bw == WL_CHANSPEC_BW_20)
66 #define IS40MHZ(pi)	((pi)->bw == WL_CHANSPEC_BW_40)
67 
68 #define PHY_GET_RFATTN(rfgain)	((rfgain) & 0x0f)
69 #define PHY_GET_PADMIX(rfgain)	(((rfgain) & 0x10) >> 4)
70 #define PHY_GET_RFGAINID(rfattn, padmix, width)	((rfattn) + ((padmix)*(width)))
71 #define PHY_SAT(x, n)		((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
72 				((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
73 #define PHY_SHIFT_ROUND(x, n)	((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
74 #define PHY_HW_ROUND(x, s)		((x >> s) + ((x >> (s-1)) & (s != 0)))
75 
76 #define CH_5G_GROUP	3
77 #define A_LOW_CHANS	0
78 #define A_MID_CHANS	1
79 #define A_HIGH_CHANS	2
80 #define CH_2G_GROUP	1
81 #define G_ALL_CHANS	0
82 
83 #define FIRST_REF5_CHANNUM	149
84 #define LAST_REF5_CHANNUM	165
85 #define	FIRST_5G_CHAN		14
86 #define	LAST_5G_CHAN		50
87 #define	FIRST_MID_5G_CHAN	14
88 #define	LAST_MID_5G_CHAN	35
89 #define	FIRST_HIGH_5G_CHAN	36
90 #define	LAST_HIGH_5G_CHAN	41
91 #define	FIRST_LOW_5G_CHAN	42
92 #define	LAST_LOW_5G_CHAN	50
93 
94 #define BASE_LOW_5G_CHAN	4900
95 #define BASE_MID_5G_CHAN	5100
96 #define BASE_HIGH_5G_CHAN	5500
97 
98 #define CHAN5G_FREQ(chan)  (5000 + chan*5)
99 #define CHAN2G_FREQ(chan)  (2407 + chan*5)
100 
101 #define TXP_FIRST_CCK		0
102 #define TXP_LAST_CCK		3
103 #define TXP_FIRST_OFDM		4
104 #define TXP_LAST_OFDM		11
105 #define TXP_FIRST_OFDM_20_CDD	12
106 #define TXP_LAST_OFDM_20_CDD	19
107 #define TXP_FIRST_MCS_20_SISO	20
108 #define TXP_LAST_MCS_20_SISO	27
109 #define TXP_FIRST_MCS_20_CDD	28
110 #define TXP_LAST_MCS_20_CDD	35
111 #define TXP_FIRST_MCS_20_STBC	36
112 #define TXP_LAST_MCS_20_STBC	43
113 #define TXP_FIRST_MCS_20_SDM	44
114 #define TXP_LAST_MCS_20_SDM	51
115 #define TXP_FIRST_OFDM_40_SISO	52
116 #define TXP_LAST_OFDM_40_SISO	59
117 #define TXP_FIRST_OFDM_40_CDD	60
118 #define TXP_LAST_OFDM_40_CDD	67
119 #define TXP_FIRST_MCS_40_SISO	68
120 #define TXP_LAST_MCS_40_SISO	75
121 #define TXP_FIRST_MCS_40_CDD	76
122 #define TXP_LAST_MCS_40_CDD	83
123 #define TXP_FIRST_MCS_40_STBC	84
124 #define TXP_LAST_MCS_40_STBC	91
125 #define TXP_FIRST_MCS_40_SDM	92
126 #define TXP_LAST_MCS_40_SDM	99
127 #define TXP_MCS_32	        100
128 #define TXP_NUM_RATES		101
129 #define ADJ_PWR_TBL_LEN		84
130 
131 #define TXP_FIRST_SISO_MCS_20	20
132 #define TXP_LAST_SISO_MCS_20	27
133 
134 #define PHY_CORE_NUM_1	1
135 #define PHY_CORE_NUM_2	2
136 #define PHY_CORE_NUM_3	3
137 #define PHY_CORE_NUM_4	4
138 #define PHY_CORE_MAX	PHY_CORE_NUM_4
139 #define PHY_CORE_0	0
140 #define PHY_CORE_1	1
141 #define PHY_CORE_2	2
142 #define PHY_CORE_3	3
143 
144 #define MA_WINDOW_SZ		8
145 
146 #define PHY_NOISE_SAMPLE_MON		1
147 #define PHY_NOISE_SAMPLE_EXTERNAL	2
148 #define PHY_NOISE_WINDOW_SZ	16
149 #define PHY_NOISE_GLITCH_INIT_MA 10
150 #define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
151 #define PHY_NOISE_STATE_MON		0x1
152 #define PHY_NOISE_STATE_EXTERNAL	0x2
153 #define PHY_NOISE_SAMPLE_LOG_NUM_NPHY	10
154 #define PHY_NOISE_SAMPLE_LOG_NUM_UCODE	9
155 
156 #define PHY_NOISE_OFFSETFACT_4322  (-103)
157 #define PHY_NOISE_MA_WINDOW_SZ	2
158 
159 #define	PHY_RSSI_TABLE_SIZE	64
160 #define RSSI_ANT_MERGE_MAX	0
161 #define RSSI_ANT_MERGE_MIN	1
162 #define RSSI_ANT_MERGE_AVG	2
163 
164 #define	PHY_TSSI_TABLE_SIZE	64
165 #define	APHY_TSSI_TABLE_SIZE	256
166 #define	TX_GAIN_TABLE_LENGTH	64
167 #define	DEFAULT_11A_TXP_IDX	24
168 #define NUM_TSSI_FRAMES        4
169 #define	NULL_TSSI		0x7f
170 #define	NULL_TSSI_W		0x7f7f
171 
172 #define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
173 
174 #define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
175 
176 #define PHY_TXPWR_MIN		10
177 #define PHY_TXPWR_MIN_NPHY	8
178 #define RADIOPWR_OVERRIDE_DEF	(-1)
179 
180 #define PWRTBL_NUM_COEFF	3
181 
182 #define SPURAVOID_DISABLE	0
183 #define SPURAVOID_AUTO		1
184 #define SPURAVOID_FORCEON	2
185 #define SPURAVOID_FORCEON2	3
186 
187 #define PHY_SW_TIMER_FAST		15
188 #define PHY_SW_TIMER_SLOW		60
189 #define PHY_SW_TIMER_GLACIAL	120
190 
191 #define PHY_PERICAL_AUTO	0
192 #define PHY_PERICAL_FULL	1
193 #define PHY_PERICAL_PARTIAL	2
194 
195 #define PHY_PERICAL_NODELAY	0
196 #define PHY_PERICAL_INIT_DELAY	5
197 #define PHY_PERICAL_ASSOC_DELAY	5
198 #define PHY_PERICAL_WDOG_DELAY	5
199 
200 #define MPHASE_TXCAL_NUMCMDS	2
201 #define PHY_PERICAL_MPHASE_PENDING(pi)	(pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
202 
203 enum {
204 	MPHASE_CAL_STATE_IDLE = 0,
205 	MPHASE_CAL_STATE_INIT = 1,
206 	MPHASE_CAL_STATE_TXPHASE0,
207 	MPHASE_CAL_STATE_TXPHASE1,
208 	MPHASE_CAL_STATE_TXPHASE2,
209 	MPHASE_CAL_STATE_TXPHASE3,
210 	MPHASE_CAL_STATE_TXPHASE4,
211 	MPHASE_CAL_STATE_TXPHASE5,
212 	MPHASE_CAL_STATE_PAPDCAL,
213 	MPHASE_CAL_STATE_RXCAL,
214 	MPHASE_CAL_STATE_RSSICAL,
215 	MPHASE_CAL_STATE_IDLETSSI
216 };
217 
218 typedef enum {
219 	CAL_FULL,
220 	CAL_RECAL,
221 	CAL_CURRECAL,
222 	CAL_DIGCAL,
223 	CAL_GCTRL,
224 	CAL_SOFT,
225 	CAL_DIGLO
226 } phy_cal_mode_t;
227 
228 #define RDR_NTIERS  1
229 #define RDR_TIER_SIZE 64
230 #define RDR_LIST_SIZE (512/3)
231 #define RDR_EPOCH_SIZE 40
232 #define RDR_NANTENNAS 2
233 #define RDR_NTIER_SIZE  RDR_LIST_SIZE
234 #define RDR_LP_BUFFER_SIZE 64
235 #define LP_LEN_HIS_SIZE 10
236 
237 #define STATIC_NUM_RF 32
238 #define STATIC_NUM_BB 9
239 
240 #define BB_MULT_MASK		0x0000ffff
241 #define BB_MULT_VALID_MASK	0x80000000
242 
243 #define CORDIC_AG	39797
244 #define	CORDIC_NI	18
245 #define	FIXED(X)	((s32)((X) << 16))
246 #define	FLOAT(X)	(((X) >= 0) ? ((((X) >> 15) + 1) >> 1) : -((((-(X)) >> 15) + 1) >> 1))
247 
248 #define PHY_CHAIN_TX_DISABLE_TEMP	115
249 #define PHY_HYSTERESIS_DELTATEMP	5
250 
251 #define PHY_BITSCNT(x)	bcm_bitcount((u8 *)&(x), sizeof(u8))
252 
253 #define MOD_PHY_REG(pi, phy_type, reg_name, field, value) \
254 	mod_phy_reg(pi, phy_type##_##reg_name, phy_type##_##reg_name##_##field##_MASK, \
255 	(value) << phy_type##_##reg_name##_##field##_##SHIFT);
256 #define READ_PHY_REG(pi, phy_type, reg_name, field) \
257 	((read_phy_reg(pi, phy_type##_##reg_name) & phy_type##_##reg_name##_##field##_##MASK)\
258 	>> phy_type##_##reg_name##_##field##_##SHIFT)
259 
260 #define	VALID_PHYTYPE(phytype)	(((uint)phytype == PHY_TYPE_N) || \
261 				((uint)phytype == PHY_TYPE_LCN))
262 
263 #define VALID_N_RADIO(radioid)	((radioid == BCM2055_ID) || (radioid == BCM2056_ID) || \
264 				(radioid == BCM2057_ID))
265 #define VALID_LCN_RADIO(radioid)	(radioid == BCM2064_ID)
266 
267 #define	VALID_RADIO(pi, radioid)	(\
268 	(ISNPHY(pi) ? VALID_N_RADIO(radioid) : false) || \
269 	(ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : false))
270 
271 #define SCAN_INPROG_PHY(pi)	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
272 #define RM_INPROG_PHY(pi)	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_RM))
273 #define PLT_INPROG_PHY(pi)	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
274 #define ASSOC_INPROG_PHY(pi)	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
275 #define SCAN_RM_IN_PROGRESS(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
276 #define PHY_MUTED(pi)		(mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
277 #define PUB_NOT_ASSOC(pi)	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
278 
279 #if defined(EXT_CBALL)
280 #define NORADIO_ENAB(pub) ((pub).radioid == NORADIO_ID)
281 #else
282 #define NORADIO_ENAB(pub) 0
283 #endif
284 
285 #define PHY_LTRN_LIST_LEN	64
286 extern u16 ltrn_list[PHY_LTRN_LIST_LEN];
287 
288 typedef struct _phy_table_info {
289 	uint table;
290 	int q;
291 	uint max;
292 } phy_table_info_t;
293 
294 typedef struct phytbl_info {
295 	const void *tbl_ptr;
296 	u32 tbl_len;
297 	u32 tbl_id;
298 	u32 tbl_offset;
299 	u32 tbl_width;
300 } phytbl_info_t;
301 
302 typedef struct {
303 	u8 curr_home_channel;
304 	u16 crsminpwrthld_40_stored;
305 	u16 crsminpwrthld_20L_stored;
306 	u16 crsminpwrthld_20U_stored;
307 	u16 init_gain_code_core1_stored;
308 	u16 init_gain_code_core2_stored;
309 	u16 init_gain_codeb_core1_stored;
310 	u16 init_gain_codeb_core2_stored;
311 	u16 init_gain_table_stored[4];
312 
313 	u16 clip1_hi_gain_code_core1_stored;
314 	u16 clip1_hi_gain_code_core2_stored;
315 	u16 clip1_hi_gain_codeb_core1_stored;
316 	u16 clip1_hi_gain_codeb_core2_stored;
317 	u16 nb_clip_thresh_core1_stored;
318 	u16 nb_clip_thresh_core2_stored;
319 	u16 init_ofdmlna2gainchange_stored[4];
320 	u16 init_ccklna2gainchange_stored[4];
321 	u16 clip1_lo_gain_code_core1_stored;
322 	u16 clip1_lo_gain_code_core2_stored;
323 	u16 clip1_lo_gain_codeb_core1_stored;
324 	u16 clip1_lo_gain_codeb_core2_stored;
325 	u16 w1_clip_thresh_core1_stored;
326 	u16 w1_clip_thresh_core2_stored;
327 	u16 radio_2056_core1_rssi_gain_stored;
328 	u16 radio_2056_core2_rssi_gain_stored;
329 	u16 energy_drop_timeout_len_stored;
330 
331 	u16 ed_crs40_assertthld0_stored;
332 	u16 ed_crs40_assertthld1_stored;
333 	u16 ed_crs40_deassertthld0_stored;
334 	u16 ed_crs40_deassertthld1_stored;
335 	u16 ed_crs20L_assertthld0_stored;
336 	u16 ed_crs20L_assertthld1_stored;
337 	u16 ed_crs20L_deassertthld0_stored;
338 	u16 ed_crs20L_deassertthld1_stored;
339 	u16 ed_crs20U_assertthld0_stored;
340 	u16 ed_crs20U_assertthld1_stored;
341 	u16 ed_crs20U_deassertthld0_stored;
342 	u16 ed_crs20U_deassertthld1_stored;
343 
344 	u16 badplcp_ma;
345 	u16 badplcp_ma_previous;
346 	u16 badplcp_ma_total;
347 	u16 badplcp_ma_list[MA_WINDOW_SZ];
348 	int badplcp_ma_index;
349 	s16 pre_badplcp_cnt;
350 	s16 bphy_pre_badplcp_cnt;
351 
352 	u16 init_gain_core1;
353 	u16 init_gain_core2;
354 	u16 init_gainb_core1;
355 	u16 init_gainb_core2;
356 	u16 init_gain_rfseq[4];
357 
358 	u16 crsminpwr0;
359 	u16 crsminpwrl0;
360 	u16 crsminpwru0;
361 
362 	s16 crsminpwr_index;
363 
364 	u16 radio_2057_core1_rssi_wb1a_gc_stored;
365 	u16 radio_2057_core2_rssi_wb1a_gc_stored;
366 	u16 radio_2057_core1_rssi_wb1g_gc_stored;
367 	u16 radio_2057_core2_rssi_wb1g_gc_stored;
368 	u16 radio_2057_core1_rssi_wb2_gc_stored;
369 	u16 radio_2057_core2_rssi_wb2_gc_stored;
370 	u16 radio_2057_core1_rssi_nb_gc_stored;
371 	u16 radio_2057_core2_rssi_nb_gc_stored;
372 
373 } interference_info_t;
374 
375 typedef struct {
376 	u16 rc_cal_ovr;
377 	u16 phycrsth1;
378 	u16 phycrsth2;
379 	u16 init_n1p1_gain;
380 	u16 p1_p2_gain;
381 	u16 n1_n2_gain;
382 	u16 n1_p1_gain;
383 	u16 div_search_gain;
384 	u16 div_p1_p2_gain;
385 	u16 div_search_gn_change;
386 	u16 table_7_2;
387 	u16 table_7_3;
388 	u16 cckshbits_gnref;
389 	u16 clip_thresh;
390 	u16 clip2_thresh;
391 	u16 clip3_thresh;
392 	u16 clip_p2_thresh;
393 	u16 clip_pwdn_thresh;
394 	u16 clip_n1p1_thresh;
395 	u16 clip_n1_pwdn_thresh;
396 	u16 bbconfig;
397 	u16 cthr_sthr_shdin;
398 	u16 energy;
399 	u16 clip_p1_p2_thresh;
400 	u16 threshold;
401 	u16 reg15;
402 	u16 reg16;
403 	u16 reg17;
404 	u16 div_srch_idx;
405 	u16 div_srch_p1_p2;
406 	u16 div_srch_gn_back;
407 	u16 ant_dwell;
408 	u16 ant_wr_settle;
409 } aci_save_gphy_t;
410 
411 typedef struct _lo_complex_t {
412 	s8 i;
413 	s8 q;
414 } lo_complex_abgphy_info_t;
415 
416 typedef struct _nphy_iq_comp {
417 	s16 a0;
418 	s16 b0;
419 	s16 a1;
420 	s16 b1;
421 } nphy_iq_comp_t;
422 
423 typedef struct _nphy_txpwrindex {
424 	s8 index;
425 	s8 index_internal;
426 	s8 index_internal_save;
427 	u16 AfectrlOverride;
428 	u16 AfeCtrlDacGain;
429 	u16 rad_gain;
430 	u8 bbmult;
431 	u16 iqcomp_a;
432 	u16 iqcomp_b;
433 	u16 locomp;
434 } phy_txpwrindex_t;
435 
436 typedef struct {
437 
438 	u16 txcal_coeffs_2G[8];
439 	u16 txcal_radio_regs_2G[8];
440 	nphy_iq_comp_t rxcal_coeffs_2G;
441 
442 	u16 txcal_coeffs_5G[8];
443 	u16 txcal_radio_regs_5G[8];
444 	nphy_iq_comp_t rxcal_coeffs_5G;
445 } txiqcal_cache_t;
446 
447 typedef struct _nphy_pwrctrl {
448 	s8 max_pwr_2g;
449 	s8 idle_targ_2g;
450 	s16 pwrdet_2g_a1;
451 	s16 pwrdet_2g_b0;
452 	s16 pwrdet_2g_b1;
453 	s8 max_pwr_5gm;
454 	s8 idle_targ_5gm;
455 	s8 max_pwr_5gh;
456 	s8 max_pwr_5gl;
457 	s16 pwrdet_5gm_a1;
458 	s16 pwrdet_5gm_b0;
459 	s16 pwrdet_5gm_b1;
460 	s16 pwrdet_5gl_a1;
461 	s16 pwrdet_5gl_b0;
462 	s16 pwrdet_5gl_b1;
463 	s16 pwrdet_5gh_a1;
464 	s16 pwrdet_5gh_b0;
465 	s16 pwrdet_5gh_b1;
466 	s8 idle_targ_5gl;
467 	s8 idle_targ_5gh;
468 	s8 idle_tssi_2g;
469 	s8 idle_tssi_5g;
470 	s8 idle_tssi;
471 	s16 a1;
472 	s16 b0;
473 	s16 b1;
474 } phy_pwrctrl_t;
475 
476 typedef struct _nphy_txgains {
477 	u16 txlpf[2];
478 	u16 txgm[2];
479 	u16 pga[2];
480 	u16 pad[2];
481 	u16 ipa[2];
482 } nphy_txgains_t;
483 
484 #define PHY_NOISEVAR_BUFSIZE 10
485 
486 typedef struct _nphy_noisevar_buf {
487 	int bufcount;
488 	int tone_id[PHY_NOISEVAR_BUFSIZE];
489 	u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
490 	u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
491 } phy_noisevar_buf_t;
492 
493 typedef struct {
494 	u16 rssical_radio_regs_2G[2];
495 	u16 rssical_phyregs_2G[12];
496 
497 	u16 rssical_radio_regs_5G[2];
498 	u16 rssical_phyregs_5G[12];
499 } rssical_cache_t;
500 
501 typedef struct {
502 
503 	u16 txiqlocal_a;
504 	u16 txiqlocal_b;
505 	u16 txiqlocal_didq;
506 	u8 txiqlocal_ei0;
507 	u8 txiqlocal_eq0;
508 	u8 txiqlocal_fi0;
509 	u8 txiqlocal_fq0;
510 
511 	u16 txiqlocal_bestcoeffs[11];
512 	u16 txiqlocal_bestcoeffs_valid;
513 
514 	u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
515 	u16 analog_gain_ref;
516 	u16 lut_begin;
517 	u16 lut_end;
518 	u16 lut_step;
519 	u16 rxcompdbm;
520 	u16 papdctrl;
521 	u16 sslpnCalibClkEnCtrl;
522 
523 	u16 rxiqcal_coeff_a0;
524 	u16 rxiqcal_coeff_b0;
525 } lcnphy_cal_results_t;
526 
527 struct shared_phy {
528 	struct phy_info *phy_head;
529 	uint unit;
530 	si_t *sih;
531 	void *physhim;
532 	uint corerev;
533 	u32 machwcap;
534 	bool up;
535 	bool clk;
536 	uint now;
537 	u16 vid;
538 	u16 did;
539 	uint chip;
540 	uint chiprev;
541 	uint chippkg;
542 	uint sromrev;
543 	uint boardtype;
544 	uint boardrev;
545 	uint boardvendor;
546 	u32 boardflags;
547 	u32 boardflags2;
548 	uint bustype;
549 	uint buscorerev;
550 	uint fast_timer;
551 	uint slow_timer;
552 	uint glacial_timer;
553 	u8 rx_antdiv;
554 	s8 phy_noise_window[MA_WINDOW_SZ];
555 	uint phy_noise_index;
556 	u8 hw_phytxchain;
557 	u8 hw_phyrxchain;
558 	u8 phytxchain;
559 	u8 phyrxchain;
560 	u8 rssi_mode;
561 	bool _rifs_phy;
562 };
563 
564 struct phy_pub {
565 	uint phy_type;
566 	uint phy_rev;
567 	u8 phy_corenum;
568 	u16 radioid;
569 	u8 radiorev;
570 	u8 radiover;
571 
572 	uint coreflags;
573 	uint ana_rev;
574 	bool abgphy_encore;
575 };
576 
577 struct phy_info_nphy;
578 typedef struct phy_info_nphy phy_info_nphy_t;
579 
580 struct phy_info_lcnphy;
581 typedef struct phy_info_lcnphy phy_info_lcnphy_t;
582 
583 struct phy_func_ptr {
584 	initfn_t init;
585 	initfn_t calinit;
586 	chansetfn_t chanset;
587 	initfn_t txpwrrecalc;
588 	longtrnfn_t longtrn;
589 	txiqccgetfn_t txiqccget;
590 	txiqccsetfn_t txiqccset;
591 	txloccgetfn_t txloccget;
592 	radioloftgetfn_t radioloftget;
593 	initfn_t carrsuppr;
594 	rxsigpwrfn_t rxsigpwr;
595 	detachfn_t detach;
596 };
597 typedef struct phy_func_ptr phy_func_ptr_t;
598 
599 struct phy_info {
600 	wlc_phy_t pubpi_ro;
601 	shared_phy_t *sh;
602 	phy_func_ptr_t pi_fptr;
603 	void *pi_ptr;
604 
605 	union {
606 		phy_info_lcnphy_t *pi_lcnphy;
607 	} u;
608 	bool user_txpwr_at_rfport;
609 
610 	d11regs_t *regs;
611 	struct phy_info *next;
612 	char *vars;
613 	wlc_phy_t pubpi;
614 
615 	bool do_initcal;
616 	bool phytest_on;
617 	bool ofdm_rateset_war;
618 	bool bf_preempt_4306;
619 	chanspec_t radio_chanspec;
620 	u8 antsel_type;
621 	u16 bw;
622 	u8 txpwr_percent;
623 	bool phy_init_por;
624 
625 	bool init_in_progress;
626 	bool initialized;
627 	bool sbtml_gm;
628 	uint refcnt;
629 	bool watchdog_override;
630 	u8 phynoise_state;
631 	uint phynoise_now;
632 	int phynoise_chan_watchdog;
633 	bool phynoise_polling;
634 	bool disable_percal;
635 	mbool measure_hold;
636 
637 	s16 txpa_2g[PWRTBL_NUM_COEFF];
638 	s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
639 	s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
640 	s16 txpa_5g_low[PWRTBL_NUM_COEFF];
641 	s16 txpa_5g_mid[PWRTBL_NUM_COEFF];
642 	s16 txpa_5g_hi[PWRTBL_NUM_COEFF];
643 
644 	u8 tx_srom_max_2g;
645 	u8 tx_srom_max_5g_low;
646 	u8 tx_srom_max_5g_mid;
647 	u8 tx_srom_max_5g_hi;
648 	u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
649 	u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
650 	u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
651 	u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
652 	u8 tx_user_target[TXP_NUM_RATES];
653 	s8 tx_power_offset[TXP_NUM_RATES];
654 	u8 tx_power_target[TXP_NUM_RATES];
655 
656 	srom_fem_t srom_fem2g;
657 	srom_fem_t srom_fem5g;
658 
659 	u8 tx_power_max;
660 	u8 tx_power_max_rate_ind;
661 	bool hwpwrctrl;
662 	u8 nphy_txpwrctrl;
663 	s8 nphy_txrx_chain;
664 	bool phy_5g_pwrgain;
665 
666 	u16 phy_wreg;
667 	u16 phy_wreg_limit;
668 
669 	s8 n_preamble_override;
670 	u8 antswitch;
671 	u8 aa2g, aa5g;
672 
673 	s8 idle_tssi[CH_5G_GROUP];
674 	s8 target_idle_tssi;
675 	s8 txpwr_est_Pout;
676 	u8 tx_power_min;
677 	u8 txpwr_limit[TXP_NUM_RATES];
678 	u8 txpwr_env_limit[TXP_NUM_RATES];
679 	u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
680 
681 	bool channel_14_wide_filter;
682 
683 	bool txpwroverride;
684 	bool txpwridx_override_aphy;
685 	s16 radiopwr_override;
686 	u16 hwpwr_txcur;
687 	u8 saved_txpwr_idx;
688 
689 	bool edcrs_threshold_lock;
690 
691 	u32 tr_R_gain_val;
692 	u32 tr_T_gain_val;
693 
694 	s16 ofdm_analog_filt_bw_override;
695 	s16 cck_analog_filt_bw_override;
696 	s16 ofdm_rccal_override;
697 	s16 cck_rccal_override;
698 	u16 extlna_type;
699 
700 	uint interference_mode_crs_time;
701 	u16 crsglitch_prev;
702 	bool interference_mode_crs;
703 
704 	u32 phy_tx_tone_freq;
705 	uint phy_lastcal;
706 	bool phy_forcecal;
707 	bool phy_fixed_noise;
708 	u32 xtalfreq;
709 	u8 pdiv;
710 	s8 carrier_suppr_disable;
711 
712 	bool phy_bphy_evm;
713 	bool phy_bphy_rfcs;
714 	s8 phy_scraminit;
715 	u8 phy_gpiosel;
716 
717 	s16 phy_txcore_disable_temp;
718 	s16 phy_txcore_enable_temp;
719 	s8 phy_tempsense_offset;
720 	bool phy_txcore_heatedup;
721 
722 	u16 radiopwr;
723 	u16 bb_atten;
724 	u16 txctl1;
725 
726 	u16 mintxbias;
727 	u16 mintxmag;
728 	lo_complex_abgphy_info_t gphy_locomp_iq[STATIC_NUM_RF][STATIC_NUM_BB];
729 	s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
730 	u16 gain_table[TX_GAIN_TABLE_LENGTH];
731 	bool loopback_gain;
732 	s16 max_lpback_gain_hdB;
733 	s16 trsw_rx_gain_hdB;
734 	u8 power_vec[8];
735 
736 	u16 rc_cal;
737 	int nrssi_table_delta;
738 	int nrssi_slope_scale;
739 	int nrssi_slope_offset;
740 	int min_rssi;
741 	int max_rssi;
742 
743 	s8 txpwridx;
744 	u8 min_txpower;
745 
746 	u8 a_band_high_disable;
747 
748 	u16 tx_vos;
749 	u16 global_tx_bb_dc_bias_loft;
750 
751 	int rf_max;
752 	int bb_max;
753 	int rf_list_size;
754 	int bb_list_size;
755 	u16 *rf_attn_list;
756 	u16 *bb_attn_list;
757 	u16 padmix_mask;
758 	u16 padmix_reg;
759 	u16 *txmag_list;
760 	uint txmag_len;
761 	bool txmag_enable;
762 
763 	s8 *a_tssi_to_dbm;
764 	s8 *m_tssi_to_dbm;
765 	s8 *l_tssi_to_dbm;
766 	s8 *h_tssi_to_dbm;
767 	u8 *hwtxpwr;
768 
769 	u16 freqtrack_saved_regs[2];
770 	int cur_interference_mode;
771 	bool hwpwrctrl_capable;
772 	bool temppwrctrl_capable;
773 
774 	uint phycal_nslope;
775 	uint phycal_noffset;
776 	uint phycal_mlo;
777 	uint phycal_txpower;
778 
779 	u8 phy_aa2g;
780 
781 	bool nphy_tableloaded;
782 	s8 nphy_rssisel;
783 	u32 nphy_bb_mult_save;
784 	u16 nphy_txiqlocal_bestc[11];
785 	bool nphy_txiqlocal_coeffsvalid;
786 	phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2];
787 	phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2];
788 	u16 cck2gpo;
789 	u32 ofdm2gpo;
790 	u32 ofdm5gpo;
791 	u32 ofdm5glpo;
792 	u32 ofdm5ghpo;
793 	u8 bw402gpo;
794 	u8 bw405gpo;
795 	u8 bw405glpo;
796 	u8 bw405ghpo;
797 	u8 cdd2gpo;
798 	u8 cdd5gpo;
799 	u8 cdd5glpo;
800 	u8 cdd5ghpo;
801 	u8 stbc2gpo;
802 	u8 stbc5gpo;
803 	u8 stbc5glpo;
804 	u8 stbc5ghpo;
805 	u8 bwdup2gpo;
806 	u8 bwdup5gpo;
807 	u8 bwdup5glpo;
808 	u8 bwdup5ghpo;
809 	u16 mcs2gpo[8];
810 	u16 mcs5gpo[8];
811 	u16 mcs5glpo[8];
812 	u16 mcs5ghpo[8];
813 	u32 nphy_rxcalparams;
814 
815 	u8 phy_spuravoid;
816 	bool phy_isspuravoid;
817 
818 	u8 phy_pabias;
819 	u8 nphy_papd_skip;
820 	u8 nphy_tssi_slope;
821 
822 	s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
823 	u8 nphy_noise_index;
824 
825 	u8 nphy_txpid2g[PHY_CORE_NUM_2];
826 	u8 nphy_txpid5g[PHY_CORE_NUM_2];
827 	u8 nphy_txpid5gl[PHY_CORE_NUM_2];
828 	u8 nphy_txpid5gh[PHY_CORE_NUM_2];
829 
830 	bool nphy_gain_boost;
831 	bool nphy_elna_gain_config;
832 	u16 old_bphy_test;
833 	u16 old_bphy_testcontrol;
834 
835 	bool phyhang_avoid;
836 
837 	bool rssical_nphy;
838 	u8 nphy_perical;
839 	uint nphy_perical_last;
840 	u8 cal_type_override;
841 	u8 mphase_cal_phase_id;
842 	u8 mphase_txcal_cmdidx;
843 	u8 mphase_txcal_numcmds;
844 	u16 mphase_txcal_bestcoeffs[11];
845 	chanspec_t nphy_txiqlocal_chanspec;
846 	chanspec_t nphy_iqcal_chanspec_2G;
847 	chanspec_t nphy_iqcal_chanspec_5G;
848 	chanspec_t nphy_rssical_chanspec_2G;
849 	chanspec_t nphy_rssical_chanspec_5G;
850 	struct wlapi_timer *phycal_timer;
851 	bool use_int_tx_iqlo_cal_nphy;
852 	bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
853 	s16 nphy_lastcal_temp;
854 
855 	txiqcal_cache_t calibration_cache;
856 	rssical_cache_t rssical_cache;
857 
858 	u8 nphy_txpwr_idx[2];
859 	u8 nphy_papd_cal_type;
860 	uint nphy_papd_last_cal;
861 	u16 nphy_papd_tx_gain_at_last_cal[2];
862 	u8 nphy_papd_cal_gain_index[2];
863 	s16 nphy_papd_epsilon_offset[2];
864 	bool nphy_papd_recal_enable;
865 	u32 nphy_papd_recal_counter;
866 	bool nphy_force_papd_cal;
867 	bool nphy_papdcomp;
868 	bool ipa2g_on;
869 	bool ipa5g_on;
870 
871 	u16 classifier_state;
872 	u16 clip_state[2];
873 	uint nphy_deaf_count;
874 	u8 rxiq_samps;
875 	u8 rxiq_antsel;
876 
877 	u16 rfctrlIntc1_save;
878 	u16 rfctrlIntc2_save;
879 	bool first_cal_after_assoc;
880 	u16 tx_rx_cal_radio_saveregs[22];
881 	u16 tx_rx_cal_phy_saveregs[15];
882 
883 	u8 nphy_cal_orig_pwr_idx[2];
884 	u8 nphy_txcal_pwr_idx[2];
885 	u8 nphy_rxcal_pwr_idx[2];
886 	u16 nphy_cal_orig_tx_gain[2];
887 	nphy_txgains_t nphy_cal_target_gain;
888 	u16 nphy_txcal_bbmult;
889 	u16 nphy_gmval;
890 
891 	u16 nphy_saved_bbconf;
892 
893 	bool nphy_gband_spurwar_en;
894 	bool nphy_gband_spurwar2_en;
895 	bool nphy_aband_spurwar_en;
896 	u16 nphy_rccal_value;
897 	u16 nphy_crsminpwr[3];
898 	phy_noisevar_buf_t nphy_saved_noisevars;
899 	bool nphy_anarxlpf_adjusted;
900 	bool nphy_crsminpwr_adjusted;
901 	bool nphy_noisevars_adjusted;
902 
903 	bool nphy_rxcal_active;
904 	u16 radar_percal_mask;
905 	bool dfs_lp_buffer_nphy;
906 
907 	u16 nphy_fineclockgatecontrol;
908 
909 	s8 rx2tx_biasentry;
910 
911 	u16 crsminpwr0;
912 	u16 crsminpwrl0;
913 	u16 crsminpwru0;
914 	s16 noise_crsminpwr_index;
915 	u16 init_gain_core1;
916 	u16 init_gain_core2;
917 	u16 init_gainb_core1;
918 	u16 init_gainb_core2;
919 	u8 aci_noise_curr_channel;
920 	u16 init_gain_rfseq[4];
921 
922 	bool radio_is_on;
923 
924 	bool nphy_sample_play_lpf_bw_ctl_ovr;
925 
926 	u16 tbl_data_hi;
927 	u16 tbl_data_lo;
928 	u16 tbl_addr;
929 
930 	uint tbl_save_id;
931 	uint tbl_save_offset;
932 
933 	u8 txpwrctrl;
934 	s8 txpwrindex[PHY_CORE_MAX];
935 
936 	u8 phycal_tempdelta;
937 	u32 mcs20_po;
938 	u32 mcs40_po;
939 };
940 
941 typedef s32 fixed;
942 
943 typedef struct _cs32 {
944 	fixed q;
945 	fixed i;
946 } cs32;
947 
948 typedef struct radio_regs {
949 	u16 address;
950 	u32 init_a;
951 	u32 init_g;
952 	u8 do_init_a;
953 	u8 do_init_g;
954 } radio_regs_t;
955 
956 typedef struct radio_20xx_regs {
957 	u16 address;
958 	u8 init;
959 	u8 do_init;
960 } radio_20xx_regs_t;
961 
962 typedef struct lcnphy_radio_regs {
963 	u16 address;
964 	u8 init_a;
965 	u8 init_g;
966 	u8 do_init_a;
967 	u8 do_init_g;
968 } lcnphy_radio_regs_t;
969 
970 extern lcnphy_radio_regs_t lcnphy_radio_regs_2064[];
971 extern lcnphy_radio_regs_t lcnphy_radio_regs_2066[];
972 extern radio_regs_t regs_2055[], regs_SYN_2056[], regs_TX_2056[],
973     regs_RX_2056[];
974 extern radio_regs_t regs_SYN_2056_A1[], regs_TX_2056_A1[], regs_RX_2056_A1[];
975 extern radio_regs_t regs_SYN_2056_rev5[], regs_TX_2056_rev5[],
976     regs_RX_2056_rev5[];
977 extern radio_regs_t regs_SYN_2056_rev6[], regs_TX_2056_rev6[],
978     regs_RX_2056_rev6[];
979 extern radio_regs_t regs_SYN_2056_rev7[], regs_TX_2056_rev7[],
980     regs_RX_2056_rev7[];
981 extern radio_regs_t regs_SYN_2056_rev8[], regs_TX_2056_rev8[],
982     regs_RX_2056_rev8[];
983 extern radio_20xx_regs_t regs_2057_rev4[], regs_2057_rev5[], regs_2057_rev5v1[];
984 extern radio_20xx_regs_t regs_2057_rev7[], regs_2057_rev8[];
985 
986 extern char *phy_getvar(phy_info_t *pi, const char *name);
987 extern int phy_getintvar(phy_info_t *pi, const char *name);
988 #define PHY_GETVAR(pi, name)	phy_getvar(pi, name)
989 #define PHY_GETINTVAR(pi, name)	phy_getintvar(pi, name)
990 
991 extern u16 read_phy_reg(phy_info_t *pi, u16 addr);
992 extern void write_phy_reg(phy_info_t *pi, u16 addr, u16 val);
993 extern void and_phy_reg(phy_info_t *pi, u16 addr, u16 val);
994 extern void or_phy_reg(phy_info_t *pi, u16 addr, u16 val);
995 extern void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val);
996 
997 extern u16 read_radio_reg(phy_info_t *pi, u16 addr);
998 extern void or_radio_reg(phy_info_t *pi, u16 addr, u16 val);
999 extern void and_radio_reg(phy_info_t *pi, u16 addr, u16 val);
1000 extern void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask,
1001 			  u16 val);
1002 extern void xor_radio_reg(phy_info_t *pi, u16 addr, u16 mask);
1003 
1004 extern void write_radio_reg(phy_info_t *pi, u16 addr, u16 val);
1005 
1006 extern void wlc_phyreg_enter(wlc_phy_t *pih);
1007 extern void wlc_phyreg_exit(wlc_phy_t *pih);
1008 extern void wlc_radioreg_enter(wlc_phy_t *pih);
1009 extern void wlc_radioreg_exit(wlc_phy_t *pih);
1010 
1011 extern void wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
1012 			       u16 tblAddr, u16 tblDataHi,
1013 			       u16 tblDatalo);
1014 extern void wlc_phy_write_table(phy_info_t *pi,
1015 				const phytbl_info_t *ptbl_info, u16 tblAddr,
1016 				u16 tblDataHi, u16 tblDatalo);
1017 extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
1018 			       u16 tblAddr, u16 tblDataHi,
1019 			       u16 tblDataLo);
1020 extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val);
1021 
1022 extern void write_phy_channel_reg(phy_info_t *pi, uint val);
1023 extern void wlc_phy_txpower_update_shm(phy_info_t *pi);
1024 
1025 extern void wlc_phy_cordic(fixed theta, cs32 *val);
1026 extern u8 wlc_phy_nbits(s32 value);
1027 extern u32 wlc_phy_sqrt_int(u32 value);
1028 extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
1029 
1030 extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi,
1031 					     radio_20xx_regs_t *radioregs);
1032 extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
1033 				    u16 core_offset);
1034 
1035 extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi);
1036 
1037 extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on);
1038 extern void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real,
1039 					s32 *eps_imag);
1040 
1041 extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi);
1042 extern void wlc_phy_cal_perical_mphase_restart(phy_info_t *pi);
1043 
1044 extern bool wlc_phy_attach_nphy(phy_info_t *pi);
1045 extern bool wlc_phy_attach_lcnphy(phy_info_t *pi);
1046 
1047 extern void wlc_phy_detach_lcnphy(phy_info_t *pi);
1048 
1049 extern void wlc_phy_init_nphy(phy_info_t *pi);
1050 extern void wlc_phy_init_lcnphy(phy_info_t *pi);
1051 
1052 extern void wlc_phy_cal_init_nphy(phy_info_t *pi);
1053 extern void wlc_phy_cal_init_lcnphy(phy_info_t *pi);
1054 
1055 extern void wlc_phy_chanspec_set_nphy(phy_info_t *pi, chanspec_t chanspec);
1056 extern void wlc_phy_chanspec_set_lcnphy(phy_info_t *pi, chanspec_t chanspec);
1057 extern void wlc_phy_chanspec_set_fixup_lcnphy(phy_info_t *pi,
1058 					      chanspec_t chanspec);
1059 extern int wlc_phy_channel2freq(uint channel);
1060 extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
1061 extern int wlc_phy_chanspec_bandrange_get(phy_info_t *, chanspec_t);
1062 
1063 extern void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, u16 mode);
1064 extern s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi);
1065 
1066 extern void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi);
1067 extern void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi);
1068 extern void wlc_phy_txpower_recalc_target_lcnphy(phy_info_t *pi);
1069 
1070 extern void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index);
1071 extern void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable);
1072 extern void wlc_lcnphy_stop_tx_tone(phy_info_t *pi);
1073 extern void wlc_lcnphy_start_tx_tone(phy_info_t *pi, s32 f_kHz,
1074 				     u16 max_val, bool iqcalmode);
1075 
1076 extern void wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan,
1077 					       u8 *max_pwr, u8 rate_id);
1078 extern void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
1079 					    u8 rate_mcs_end,
1080 					    u8 rate_ofdm_start);
1081 extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power,
1082 					    u8 rate_ofdm_start,
1083 					    u8 rate_ofdm_end,
1084 					    u8 rate_mcs_start);
1085 
1086 extern u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode);
1087 extern s16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode);
1088 extern s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode);
1089 extern s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode);
1090 extern void wlc_phy_carrier_suppress_lcnphy(phy_info_t *pi);
1091 extern void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel);
1092 extern void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode);
1093 extern void wlc_2064_vco_cal(phy_info_t *pi);
1094 
1095 extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
1096 extern u32 wlc_phy_qdiv_roundup(u32 dividend, u32 divisor,
1097 				   u8 precision);
1098 
1099 #define LCNPHY_TBL_ID_PAPDCOMPDELTATBL	0x18
1100 #define LCNPHY_TX_POWER_TABLE_SIZE	128
1101 #define LCNPHY_MAX_TX_POWER_INDEX	(LCNPHY_TX_POWER_TABLE_SIZE - 1)
1102 #define LCNPHY_TBL_ID_TXPWRCTL 	0x07
1103 #define LCNPHY_TX_PWR_CTRL_OFF	0
1104 #define LCNPHY_TX_PWR_CTRL_SW		(0x1 << 15)
1105 #define LCNPHY_TX_PWR_CTRL_HW         ((0x1 << 15) | \
1106 					(0x1 << 14) | \
1107 					(0x1 << 13))
1108 
1109 #define LCNPHY_TX_PWR_CTRL_TEMPBASED	0xE001
1110 
1111 extern void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti);
1112 extern void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti);
1113 extern void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, u16 a, u16 b);
1114 extern void wlc_lcnphy_set_tx_locc(phy_info_t *pi, u16 didq);
1115 extern void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, u16 *a, u16 *b);
1116 extern u16 wlc_lcnphy_get_tx_locc(phy_info_t *pi);
1117 extern void wlc_lcnphy_get_radio_loft(phy_info_t *pi, u8 *ei0,
1118 				      u8 *eq0, u8 *fi0, u8 *fq0);
1119 extern void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode);
1120 extern void wlc_lcnphy_deaf_mode(phy_info_t *pi, bool mode);
1121 extern bool wlc_phy_tpc_isenabled_lcnphy(phy_info_t *pi);
1122 extern void wlc_lcnphy_tx_pwr_update_npt(phy_info_t *pi);
1123 extern s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
1124 extern void wlc_lcnphy_get_tssi(phy_info_t *pi, s8 *ofdm_pwr,
1125 				s8 *cck_pwr);
1126 extern void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi);
1127 
1128 extern s32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, s32 gain_index);
1129 
1130 #define NPHY_MAX_HPVGA1_INDEX		10
1131 #define NPHY_DEF_HPVGA1_INDEXLIMIT	7
1132 
1133 typedef struct _phy_iq_est {
1134 	s32 iq_prod;
1135 	u32 i_pwr;
1136 	u32 q_pwr;
1137 } phy_iq_est_t;
1138 
1139 extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable);
1140 extern void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode);
1141 
1142 #define wlc_phy_write_table_nphy(pi, pti)	wlc_phy_write_table(pi, pti, 0x72, \
1143 	0x74, 0x73)
1144 #define wlc_phy_read_table_nphy(pi, pti)	wlc_phy_read_table(pi, pti, 0x72, \
1145 	0x74, 0x73)
1146 #define wlc_nphy_table_addr(pi, id, off)	wlc_phy_table_addr((pi), (id), (off), \
1147 	0x72, 0x74, 0x73)
1148 #define wlc_nphy_table_data_write(pi, w, v)	wlc_phy_table_data_write((pi), (w), (v))
1149 
1150 extern void wlc_phy_table_read_nphy(phy_info_t *pi, u32, u32 l, u32 o,
1151 				    u32 w, void *d);
1152 extern void wlc_phy_table_write_nphy(phy_info_t *pi, u32, u32, u32,
1153 				     u32, const void *);
1154 
1155 #define	PHY_IPA(pi) \
1156 	((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
1157 	 (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
1158 
1159 #define WLC_PHY_WAR_PR51571(pi) \
1160 	if (((pi)->sh->bustype == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \
1161 		(void)R_REG(&(pi)->regs->maccontrol)
1162 
1163 extern void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, u8 caltype);
1164 extern void wlc_phy_aci_reset_nphy(phy_info_t *pi);
1165 extern void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en);
1166 
1167 extern u8 wlc_phy_get_chan_freq_range_nphy(phy_info_t *pi, uint chan);
1168 extern void wlc_phy_switch_radio_nphy(phy_info_t *pi, bool on);
1169 
1170 extern void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi);
1171 
1172 extern void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd);
1173 extern s16 wlc_phy_tempsense_nphy(phy_info_t *pi);
1174 
1175 extern u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val);
1176 
1177 extern void wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est,
1178 				   u16 num_samps, u8 wait_time,
1179 				   u8 wait_for_crs);
1180 
1181 extern void wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, u8 write,
1182 				      nphy_iq_comp_t *comp);
1183 extern void wlc_phy_aci_and_noise_reduction_nphy(phy_info_t *pi);
1184 
1185 extern void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask);
1186 extern u8 wlc_phy_rxcore_getstate_nphy(wlc_phy_t *pih);
1187 
1188 extern void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type);
1189 extern void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi);
1190 extern void wlc_phy_txpwr_apply_nphy(phy_info_t *pi);
1191 extern void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi);
1192 extern u16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi);
1193 
1194 extern nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi);
1195 extern int wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
1196 				   bool full, bool m);
1197 extern int wlc_phy_cal_rxiq_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
1198 				 u8 type, bool d);
1199 extern void wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask,
1200 				     s8 txpwrindex, bool res);
1201 extern void wlc_phy_rssisel_nphy(phy_info_t *pi, u8 core, u8 rssi_type);
1202 extern int wlc_phy_poll_rssi_nphy(phy_info_t *pi, u8 rssi_type,
1203 				  s32 *rssi_buf, u8 nsamps);
1204 extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi);
1205 extern int wlc_phy_aci_scan_nphy(phy_info_t *pi);
1206 extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, s32 dBm_targetpower,
1207 					bool debug);
1208 extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
1209 				u8 mode, u8, bool);
1210 extern void wlc_phy_stopplayback_nphy(phy_info_t *pi);
1211 extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, s32 *qdBm_pwrbuf,
1212 				     u8 num_samps);
1213 extern void wlc_phy_radio205x_vcocal_nphy(phy_info_t *pi);
1214 
1215 extern int wlc_phy_rssi_compute_nphy(phy_info_t *pi, wlc_d11rxhdr_t *wlc_rxh);
1216 
1217 #define NPHY_TESTPATTERN_BPHY_EVM   0
1218 #define NPHY_TESTPATTERN_BPHY_RFCS  1
1219 
1220 extern void wlc_phy_nphy_tkip_rifs_war(phy_info_t *pi, u8 rifs);
1221 
1222 void wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset,
1223 				s8 *ofdmoffset);
1224 extern s8 wlc_phy_upd_rssi_offset(phy_info_t *pi, s8 rssi,
1225 				    chanspec_t chanspec);
1226 
1227 extern bool wlc_phy_n_txpower_ipa_ison(phy_info_t *pih);
1228 #endif				/* _wlc_phy_int_h_ */
1229