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Searched refs:reg_set (Results 1 – 17 of 17) sorted by relevance

/linux-2.6.39/arch/arm/mach-omap2/
Dpm-debug.c267 int reg_set = (int)s->private; in pm_dbg_show_regs() local
273 if (reg_set == 0) { in pm_dbg_show_regs()
278 ptr = pm_dbg_reg_set[reg_set - 1]; in pm_dbg_show_regs()
343 int pm_dbg_regset_save(int reg_set) in pm_dbg_regset_save() argument
345 if (pm_dbg_reg_set[reg_set-1] == NULL) in pm_dbg_regset_save()
348 pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]); in pm_dbg_regset_save()
491 int pm_dbg_regset_init(int reg_set) in pm_dbg_regset_init() argument
498 if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS || in pm_dbg_regset_init()
499 pm_dbg_reg_set[reg_set-1] != NULL) in pm_dbg_regset_init()
502 pm_dbg_reg_set[reg_set-1] = in pm_dbg_regset_init()
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Dpm.h82 extern int pm_dbg_regset_save(int reg_set);
83 extern int pm_dbg_regset_init(int reg_set);
86 #define pm_dbg_regset_save(reg_set) do {} while (0); argument
87 #define pm_dbg_regset_init(reg_set) do {} while (0); argument
/linux-2.6.39/drivers/scsi/mvsas/
Dmv_sas.h84 #define SATA_RECEIVED_FIS_LIST(reg_set) \ argument
85 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
86 #define SATA_RECEIVED_SDB_FIS(reg_set) \ argument
87 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
88 #define SATA_RECEIVED_D2H_FIS(reg_set) \ argument
89 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
90 #define SATA_RECEIVED_PIO_FIS(reg_set) \ argument
91 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
92 #define SATA_RECEIVED_DMA_FIS(reg_set) \ argument
93 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
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Dmv_94xx.c373 u8 reg_set = *tfs; in mvs_94xx_free_reg_set() local
378 mvi->sata_reg_set &= ~bit(reg_set); in mvs_94xx_free_reg_set()
379 if (reg_set < 32) { in mvs_94xx_free_reg_set()
380 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set); in mvs_94xx_free_reg_set()
385 w_reg_set_enable(reg_set, mvi->sata_reg_set); in mvs_94xx_free_reg_set()
623 static void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, in mvs_94xx_clear_srs_irq() argument
Dmv_64xx.c147 void mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) in mvs_64xx_clear_srs_irq() argument
159 if (tmp & (1 << (reg_set % 32))) { in mvs_64xx_clear_srs_irq()
161 reg_set); in mvs_64xx_clear_srs_irq()
162 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); in mvs_64xx_clear_srs_irq()
/linux-2.6.39/drivers/scsi/megaraid/
Dmegaraid_sas_fusion.c665 instance->instancet->disable_intr(instance->reg_set); in megasas_ioc_init_fusion()
668 if (readl(&instance->reg_set->doorbell) & 1) in megasas_ioc_init_fusion()
675 req_desc->u.high, instance->reg_set); in megasas_ioc_init_fusion()
897 struct megasas_register_set __iomem *reg_set; in megasas_init_adapter_fusion() local
904 reg_set = instance->reg_set; in megasas_init_adapter_fusion()
910 instance->instancet->read_fw_status_reg(reg_set) & 0x00FFFF; in megasas_init_adapter_fusion()
1616 instance->reg_set); in megasas_build_and_issue_cmd_fusion()
1750 &instance->reg_set->reply_post_host_index); in complete_cmd_fusion()
1790 mfiStatus = instance->instancet->clear_intr(instance->reg_set); in megasas_isr_fusion()
1802 instance->reg_set) & MFI_STATE_MASK; in megasas_isr_fusion()
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Dmegaraid_sas_base.c142 struct megasas_register_set __iomem *reg_set);
172 cmd->frame_phys_addr, 0, instance->reg_set); in megasas_issue_dcmd()
744 struct megasas_register_set __iomem *reg_set) in megasas_adp_reset_gen2() argument
748 u32 *seq_offset = &reg_set->seq_offset; in megasas_adp_reset_gen2()
749 u32 *hostdiag_offset = &reg_set->host_diag; in megasas_adp_reset_gen2()
752 seq_offset = &reg_set->fusion_seq_offset; in megasas_adp_reset_gen2()
753 hostdiag_offset = &reg_set->fusion_host_diag; in megasas_adp_reset_gen2()
1434 cmd->frame_count-1, instance->reg_set); in megasas_build_and_issue_cmd()
1586 writel(MFI_STOP_ADP, &instance->reg_set->doorbell); in megaraid_sas_kill_hba()
1588 writel(MFI_STOP_ADP, &instance->reg_set->inbound_doorbell); in megaraid_sas_kill_hba()
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Dmegaraid_sas.h1290 struct megasas_register_set __iomem *reg_set; member
/linux-2.6.39/drivers/gpio/
Dbasic_mmio_gpio.c67 void __iomem *reg_set; member
153 if (bgc->reg_set) { in bgpio_set()
155 bgpio_out(bgc, bgc->reg_set, mask); in bgpio_set()
224 bgc->reg_set = devm_ioremap(dev, res_set->start, dat_sz); in bgpio_probe()
226 if (!bgc->reg_set || !bgc->reg_clr) in bgpio_probe()
/linux-2.6.39/drivers/media/video/
Drj54n1cb0c.c458 static int reg_set(struct i2c_client *client, const u16 reg, in reg_set() function
499 return reg_set(client, RJ54N1_STILL_CONTROL, (!enable) << 7, 0x80); in rj54n1_s_stream()
903 ret = reg_set(client, RJ54N1_OCLK_DSP, 1, 1); in rj54n1_set_clock()
1052 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_s_fmt()
1057 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_s_fmt()
1062 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_s_fmt()
1067 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_s_fmt()
1072 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_s_fmt()
1079 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_s_fmt()
1086 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_s_fmt()
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Dmt9m111.c123 #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) macro
382 ret = reg_set(RESET, MT9M111_RESET_CHIP_ENABLE); in mt9m111_enable()
392 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_reset()
394 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); in mt9m111_reset()
738 ret = reg_set(READ_MODE_B, mask); in mt9m111_set_flip()
743 ret = reg_set(READ_MODE_A, mask); in mt9m111_set_flip()
787 ret = reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); in mt9m111_set_autoexposure()
803 ret = reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); in mt9m111_set_autowhitebalance()
Dmt9t031.c94 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
171 ret = reg_set(client, MT9T031_OUTPUT_CONTROL, 2); in mt9t031_s_stream()
194 reg_set(client, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000); in mt9t031_set_bus_param()
333 ret = reg_set(client, MT9T031_OUTPUT_CONTROL, 1); in mt9t031_set_params()
588 data = reg_set(client, MT9T031_READ_MODE_2, 0x8000); in mt9t031_s_ctrl()
596 data = reg_set(client, MT9T031_READ_MODE_2, 0x4000); in mt9t031_s_ctrl()
Dmt9v022.c129 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
169 ret = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x3); in mt9v022_init()
635 data = reg_set(client, MT9V022_READ_MODE, 0x10); in mt9v022_s_ctrl()
643 data = reg_set(client, MT9V022_READ_MODE, 0x20); in mt9v022_s_ctrl()
700 data = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x2); in mt9v022_s_ctrl()
708 data = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x1); in mt9v022_s_ctrl()
Dak881x.c50 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
198 reg_set(client, AK881X_VIDEO_PROCESS1, vp1, 0xf); in ak881x_s_std_output()
Dmt9m001.c115 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
511 data = reg_set(client, MT9M001_READ_OPTIONS2, 0x8000); in mt9m001_s_ctrl()
/linux-2.6.39/arch/powerpc/boot/
Dmpsc.c128 int n, reg_set; in mpsc_console_init() local
147 reg_set = (int)v; in mpsc_console_init()
149 mpscintr_base += (reg_set == 0) ? 0x4 : 0xc; in mpsc_console_init()
/linux-2.6.39/arch/ia64/include/asm/
Dperfmon.h86 unsigned short reg_set; /* event set for this register */ member