1 #ifndef __bif_dma_defs_asm_h 2 #define __bif_dma_defs_asm_h 3 4 /* 5 * This file is autogenerated from 6 * file: ../../inst/bif/rtl/bif_dma_regs.r 7 * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp 8 * last modfied: Mon Apr 11 16:06:33 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r 11 * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17 #ifndef REG_FIELD 18 #define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20 #define REG_FIELD_X_( value, shift ) ((value) << shift) 21 #endif 22 23 #ifndef REG_STATE 24 #define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26 #define REG_STATE_X_( k, shift ) (k << shift) 27 #endif 28 29 #ifndef REG_MASK 30 #define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33 #endif 34 35 #ifndef REG_LSB 36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37 #endif 38 39 #ifndef REG_BIT 40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41 #endif 42 43 #ifndef REG_ADDR 44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46 #endif 47 48 #ifndef REG_ADDR_VECT 49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54 #endif 55 56 /* Register rw_ch0_ctrl, scope bif_dma, type rw */ 57 #define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0 58 #define reg_bif_dma_rw_ch0_ctrl___bw___width 2 59 #define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2 60 #define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1 61 #define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2 62 #define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3 63 #define reg_bif_dma_rw_ch0_ctrl___cont___width 1 64 #define reg_bif_dma_rw_ch0_ctrl___cont___bit 3 65 #define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4 66 #define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1 67 #define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4 68 #define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5 69 #define reg_bif_dma_rw_ch0_ctrl___cnt___width 1 70 #define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5 71 #define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6 72 #define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3 73 #define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9 74 #define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2 75 #define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11 76 #define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3 77 #define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14 78 #define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2 79 #define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16 80 #define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2 81 #define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18 82 #define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1 83 #define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18 84 #define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19 85 #define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1 86 #define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19 87 #define reg_bif_dma_rw_ch0_ctrl_offset 0 88 89 /* Register rw_ch0_addr, scope bif_dma, type rw */ 90 #define reg_bif_dma_rw_ch0_addr___addr___lsb 0 91 #define reg_bif_dma_rw_ch0_addr___addr___width 32 92 #define reg_bif_dma_rw_ch0_addr_offset 4 93 94 /* Register rw_ch0_start, scope bif_dma, type rw */ 95 #define reg_bif_dma_rw_ch0_start___run___lsb 0 96 #define reg_bif_dma_rw_ch0_start___run___width 1 97 #define reg_bif_dma_rw_ch0_start___run___bit 0 98 #define reg_bif_dma_rw_ch0_start_offset 8 99 100 /* Register rw_ch0_cnt, scope bif_dma, type rw */ 101 #define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0 102 #define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16 103 #define reg_bif_dma_rw_ch0_cnt_offset 12 104 105 /* Register r_ch0_stat, scope bif_dma, type r */ 106 #define reg_bif_dma_r_ch0_stat___cnt___lsb 0 107 #define reg_bif_dma_r_ch0_stat___cnt___width 16 108 #define reg_bif_dma_r_ch0_stat___run___lsb 31 109 #define reg_bif_dma_r_ch0_stat___run___width 1 110 #define reg_bif_dma_r_ch0_stat___run___bit 31 111 #define reg_bif_dma_r_ch0_stat_offset 16 112 113 /* Register rw_ch1_ctrl, scope bif_dma, type rw */ 114 #define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0 115 #define reg_bif_dma_rw_ch1_ctrl___bw___width 2 116 #define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2 117 #define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1 118 #define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2 119 #define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3 120 #define reg_bif_dma_rw_ch1_ctrl___cont___width 1 121 #define reg_bif_dma_rw_ch1_ctrl___cont___bit 3 122 #define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4 123 #define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1 124 #define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4 125 #define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5 126 #define reg_bif_dma_rw_ch1_ctrl___cnt___width 1 127 #define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5 128 #define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6 129 #define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3 130 #define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9 131 #define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2 132 #define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11 133 #define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3 134 #define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14 135 #define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2 136 #define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16 137 #define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2 138 #define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18 139 #define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1 140 #define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18 141 #define reg_bif_dma_rw_ch1_ctrl_offset 32 142 143 /* Register rw_ch1_addr, scope bif_dma, type rw */ 144 #define reg_bif_dma_rw_ch1_addr___addr___lsb 0 145 #define reg_bif_dma_rw_ch1_addr___addr___width 32 146 #define reg_bif_dma_rw_ch1_addr_offset 36 147 148 /* Register rw_ch1_start, scope bif_dma, type rw */ 149 #define reg_bif_dma_rw_ch1_start___run___lsb 0 150 #define reg_bif_dma_rw_ch1_start___run___width 1 151 #define reg_bif_dma_rw_ch1_start___run___bit 0 152 #define reg_bif_dma_rw_ch1_start_offset 40 153 154 /* Register rw_ch1_cnt, scope bif_dma, type rw */ 155 #define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0 156 #define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16 157 #define reg_bif_dma_rw_ch1_cnt_offset 44 158 159 /* Register r_ch1_stat, scope bif_dma, type r */ 160 #define reg_bif_dma_r_ch1_stat___cnt___lsb 0 161 #define reg_bif_dma_r_ch1_stat___cnt___width 16 162 #define reg_bif_dma_r_ch1_stat___run___lsb 31 163 #define reg_bif_dma_r_ch1_stat___run___width 1 164 #define reg_bif_dma_r_ch1_stat___run___bit 31 165 #define reg_bif_dma_r_ch1_stat_offset 48 166 167 /* Register rw_ch2_ctrl, scope bif_dma, type rw */ 168 #define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0 169 #define reg_bif_dma_rw_ch2_ctrl___bw___width 2 170 #define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2 171 #define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1 172 #define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2 173 #define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3 174 #define reg_bif_dma_rw_ch2_ctrl___cont___width 1 175 #define reg_bif_dma_rw_ch2_ctrl___cont___bit 3 176 #define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4 177 #define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1 178 #define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4 179 #define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5 180 #define reg_bif_dma_rw_ch2_ctrl___cnt___width 1 181 #define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5 182 #define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6 183 #define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3 184 #define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9 185 #define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2 186 #define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11 187 #define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3 188 #define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14 189 #define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2 190 #define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16 191 #define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2 192 #define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18 193 #define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1 194 #define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18 195 #define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19 196 #define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1 197 #define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19 198 #define reg_bif_dma_rw_ch2_ctrl_offset 64 199 200 /* Register rw_ch2_addr, scope bif_dma, type rw */ 201 #define reg_bif_dma_rw_ch2_addr___addr___lsb 0 202 #define reg_bif_dma_rw_ch2_addr___addr___width 32 203 #define reg_bif_dma_rw_ch2_addr_offset 68 204 205 /* Register rw_ch2_start, scope bif_dma, type rw */ 206 #define reg_bif_dma_rw_ch2_start___run___lsb 0 207 #define reg_bif_dma_rw_ch2_start___run___width 1 208 #define reg_bif_dma_rw_ch2_start___run___bit 0 209 #define reg_bif_dma_rw_ch2_start_offset 72 210 211 /* Register rw_ch2_cnt, scope bif_dma, type rw */ 212 #define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0 213 #define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16 214 #define reg_bif_dma_rw_ch2_cnt_offset 76 215 216 /* Register r_ch2_stat, scope bif_dma, type r */ 217 #define reg_bif_dma_r_ch2_stat___cnt___lsb 0 218 #define reg_bif_dma_r_ch2_stat___cnt___width 16 219 #define reg_bif_dma_r_ch2_stat___run___lsb 31 220 #define reg_bif_dma_r_ch2_stat___run___width 1 221 #define reg_bif_dma_r_ch2_stat___run___bit 31 222 #define reg_bif_dma_r_ch2_stat_offset 80 223 224 /* Register rw_ch3_ctrl, scope bif_dma, type rw */ 225 #define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0 226 #define reg_bif_dma_rw_ch3_ctrl___bw___width 2 227 #define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2 228 #define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1 229 #define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2 230 #define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3 231 #define reg_bif_dma_rw_ch3_ctrl___cont___width 1 232 #define reg_bif_dma_rw_ch3_ctrl___cont___bit 3 233 #define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4 234 #define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1 235 #define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4 236 #define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5 237 #define reg_bif_dma_rw_ch3_ctrl___cnt___width 1 238 #define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5 239 #define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6 240 #define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3 241 #define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9 242 #define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2 243 #define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11 244 #define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3 245 #define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14 246 #define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2 247 #define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16 248 #define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2 249 #define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18 250 #define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1 251 #define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18 252 #define reg_bif_dma_rw_ch3_ctrl_offset 96 253 254 /* Register rw_ch3_addr, scope bif_dma, type rw */ 255 #define reg_bif_dma_rw_ch3_addr___addr___lsb 0 256 #define reg_bif_dma_rw_ch3_addr___addr___width 32 257 #define reg_bif_dma_rw_ch3_addr_offset 100 258 259 /* Register rw_ch3_start, scope bif_dma, type rw */ 260 #define reg_bif_dma_rw_ch3_start___run___lsb 0 261 #define reg_bif_dma_rw_ch3_start___run___width 1 262 #define reg_bif_dma_rw_ch3_start___run___bit 0 263 #define reg_bif_dma_rw_ch3_start_offset 104 264 265 /* Register rw_ch3_cnt, scope bif_dma, type rw */ 266 #define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0 267 #define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16 268 #define reg_bif_dma_rw_ch3_cnt_offset 108 269 270 /* Register r_ch3_stat, scope bif_dma, type r */ 271 #define reg_bif_dma_r_ch3_stat___cnt___lsb 0 272 #define reg_bif_dma_r_ch3_stat___cnt___width 16 273 #define reg_bif_dma_r_ch3_stat___run___lsb 31 274 #define reg_bif_dma_r_ch3_stat___run___width 1 275 #define reg_bif_dma_r_ch3_stat___run___bit 31 276 #define reg_bif_dma_r_ch3_stat_offset 112 277 278 /* Register rw_intr_mask, scope bif_dma, type rw */ 279 #define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0 280 #define reg_bif_dma_rw_intr_mask___ext_dma0___width 1 281 #define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0 282 #define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1 283 #define reg_bif_dma_rw_intr_mask___ext_dma1___width 1 284 #define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1 285 #define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2 286 #define reg_bif_dma_rw_intr_mask___ext_dma2___width 1 287 #define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2 288 #define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3 289 #define reg_bif_dma_rw_intr_mask___ext_dma3___width 1 290 #define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3 291 #define reg_bif_dma_rw_intr_mask_offset 128 292 293 /* Register rw_ack_intr, scope bif_dma, type rw */ 294 #define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0 295 #define reg_bif_dma_rw_ack_intr___ext_dma0___width 1 296 #define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0 297 #define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1 298 #define reg_bif_dma_rw_ack_intr___ext_dma1___width 1 299 #define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1 300 #define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2 301 #define reg_bif_dma_rw_ack_intr___ext_dma2___width 1 302 #define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2 303 #define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3 304 #define reg_bif_dma_rw_ack_intr___ext_dma3___width 1 305 #define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3 306 #define reg_bif_dma_rw_ack_intr_offset 132 307 308 /* Register r_intr, scope bif_dma, type r */ 309 #define reg_bif_dma_r_intr___ext_dma0___lsb 0 310 #define reg_bif_dma_r_intr___ext_dma0___width 1 311 #define reg_bif_dma_r_intr___ext_dma0___bit 0 312 #define reg_bif_dma_r_intr___ext_dma1___lsb 1 313 #define reg_bif_dma_r_intr___ext_dma1___width 1 314 #define reg_bif_dma_r_intr___ext_dma1___bit 1 315 #define reg_bif_dma_r_intr___ext_dma2___lsb 2 316 #define reg_bif_dma_r_intr___ext_dma2___width 1 317 #define reg_bif_dma_r_intr___ext_dma2___bit 2 318 #define reg_bif_dma_r_intr___ext_dma3___lsb 3 319 #define reg_bif_dma_r_intr___ext_dma3___width 1 320 #define reg_bif_dma_r_intr___ext_dma3___bit 3 321 #define reg_bif_dma_r_intr_offset 136 322 323 /* Register r_masked_intr, scope bif_dma, type r */ 324 #define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0 325 #define reg_bif_dma_r_masked_intr___ext_dma0___width 1 326 #define reg_bif_dma_r_masked_intr___ext_dma0___bit 0 327 #define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1 328 #define reg_bif_dma_r_masked_intr___ext_dma1___width 1 329 #define reg_bif_dma_r_masked_intr___ext_dma1___bit 1 330 #define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2 331 #define reg_bif_dma_r_masked_intr___ext_dma2___width 1 332 #define reg_bif_dma_r_masked_intr___ext_dma2___bit 2 333 #define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3 334 #define reg_bif_dma_r_masked_intr___ext_dma3___width 1 335 #define reg_bif_dma_r_masked_intr___ext_dma3___bit 3 336 #define reg_bif_dma_r_masked_intr_offset 140 337 338 /* Register rw_pin0_cfg, scope bif_dma, type rw */ 339 #define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0 340 #define reg_bif_dma_rw_pin0_cfg___master_ch___width 2 341 #define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2 342 #define reg_bif_dma_rw_pin0_cfg___master_mode___width 3 343 #define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5 344 #define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2 345 #define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7 346 #define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3 347 #define reg_bif_dma_rw_pin0_cfg_offset 160 348 349 /* Register rw_pin1_cfg, scope bif_dma, type rw */ 350 #define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0 351 #define reg_bif_dma_rw_pin1_cfg___master_ch___width 2 352 #define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2 353 #define reg_bif_dma_rw_pin1_cfg___master_mode___width 3 354 #define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5 355 #define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2 356 #define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7 357 #define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3 358 #define reg_bif_dma_rw_pin1_cfg_offset 164 359 360 /* Register rw_pin2_cfg, scope bif_dma, type rw */ 361 #define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0 362 #define reg_bif_dma_rw_pin2_cfg___master_ch___width 2 363 #define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2 364 #define reg_bif_dma_rw_pin2_cfg___master_mode___width 3 365 #define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5 366 #define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2 367 #define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7 368 #define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3 369 #define reg_bif_dma_rw_pin2_cfg_offset 168 370 371 /* Register rw_pin3_cfg, scope bif_dma, type rw */ 372 #define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0 373 #define reg_bif_dma_rw_pin3_cfg___master_ch___width 2 374 #define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2 375 #define reg_bif_dma_rw_pin3_cfg___master_mode___width 3 376 #define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5 377 #define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2 378 #define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7 379 #define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3 380 #define reg_bif_dma_rw_pin3_cfg_offset 172 381 382 /* Register rw_pin4_cfg, scope bif_dma, type rw */ 383 #define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0 384 #define reg_bif_dma_rw_pin4_cfg___master_ch___width 2 385 #define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2 386 #define reg_bif_dma_rw_pin4_cfg___master_mode___width 3 387 #define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5 388 #define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2 389 #define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7 390 #define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3 391 #define reg_bif_dma_rw_pin4_cfg_offset 176 392 393 /* Register rw_pin5_cfg, scope bif_dma, type rw */ 394 #define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0 395 #define reg_bif_dma_rw_pin5_cfg___master_ch___width 2 396 #define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2 397 #define reg_bif_dma_rw_pin5_cfg___master_mode___width 3 398 #define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5 399 #define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2 400 #define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7 401 #define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3 402 #define reg_bif_dma_rw_pin5_cfg_offset 180 403 404 /* Register rw_pin6_cfg, scope bif_dma, type rw */ 405 #define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0 406 #define reg_bif_dma_rw_pin6_cfg___master_ch___width 2 407 #define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2 408 #define reg_bif_dma_rw_pin6_cfg___master_mode___width 3 409 #define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5 410 #define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2 411 #define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7 412 #define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3 413 #define reg_bif_dma_rw_pin6_cfg_offset 184 414 415 /* Register rw_pin7_cfg, scope bif_dma, type rw */ 416 #define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0 417 #define reg_bif_dma_rw_pin7_cfg___master_ch___width 2 418 #define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2 419 #define reg_bif_dma_rw_pin7_cfg___master_mode___width 3 420 #define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5 421 #define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2 422 #define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7 423 #define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3 424 #define reg_bif_dma_rw_pin7_cfg_offset 188 425 426 /* Register r_pin_stat, scope bif_dma, type r */ 427 #define reg_bif_dma_r_pin_stat___pin0___lsb 0 428 #define reg_bif_dma_r_pin_stat___pin0___width 1 429 #define reg_bif_dma_r_pin_stat___pin0___bit 0 430 #define reg_bif_dma_r_pin_stat___pin1___lsb 1 431 #define reg_bif_dma_r_pin_stat___pin1___width 1 432 #define reg_bif_dma_r_pin_stat___pin1___bit 1 433 #define reg_bif_dma_r_pin_stat___pin2___lsb 2 434 #define reg_bif_dma_r_pin_stat___pin2___width 1 435 #define reg_bif_dma_r_pin_stat___pin2___bit 2 436 #define reg_bif_dma_r_pin_stat___pin3___lsb 3 437 #define reg_bif_dma_r_pin_stat___pin3___width 1 438 #define reg_bif_dma_r_pin_stat___pin3___bit 3 439 #define reg_bif_dma_r_pin_stat___pin4___lsb 4 440 #define reg_bif_dma_r_pin_stat___pin4___width 1 441 #define reg_bif_dma_r_pin_stat___pin4___bit 4 442 #define reg_bif_dma_r_pin_stat___pin5___lsb 5 443 #define reg_bif_dma_r_pin_stat___pin5___width 1 444 #define reg_bif_dma_r_pin_stat___pin5___bit 5 445 #define reg_bif_dma_r_pin_stat___pin6___lsb 6 446 #define reg_bif_dma_r_pin_stat___pin6___width 1 447 #define reg_bif_dma_r_pin_stat___pin6___bit 6 448 #define reg_bif_dma_r_pin_stat___pin7___lsb 7 449 #define reg_bif_dma_r_pin_stat___pin7___width 1 450 #define reg_bif_dma_r_pin_stat___pin7___bit 7 451 #define reg_bif_dma_r_pin_stat_offset 192 452 453 454 /* Constants */ 455 #define regk_bif_dma_as_master 0x00000001 456 #define regk_bif_dma_as_slave 0x00000001 457 #define regk_bif_dma_burst1 0x00000000 458 #define regk_bif_dma_burst8 0x00000001 459 #define regk_bif_dma_bw16 0x00000001 460 #define regk_bif_dma_bw32 0x00000002 461 #define regk_bif_dma_bw8 0x00000000 462 #define regk_bif_dma_dack 0x00000006 463 #define regk_bif_dma_dack_inv 0x00000007 464 #define regk_bif_dma_force 0x00000001 465 #define regk_bif_dma_hi 0x00000003 466 #define regk_bif_dma_inv 0x00000003 467 #define regk_bif_dma_lo 0x00000002 468 #define regk_bif_dma_master 0x00000001 469 #define regk_bif_dma_no 0x00000000 470 #define regk_bif_dma_norm 0x00000002 471 #define regk_bif_dma_off 0x00000000 472 #define regk_bif_dma_rw_ch0_ctrl_default 0x00000000 473 #define regk_bif_dma_rw_ch0_start_default 0x00000000 474 #define regk_bif_dma_rw_ch1_ctrl_default 0x00000000 475 #define regk_bif_dma_rw_ch1_start_default 0x00000000 476 #define regk_bif_dma_rw_ch2_ctrl_default 0x00000000 477 #define regk_bif_dma_rw_ch2_start_default 0x00000000 478 #define regk_bif_dma_rw_ch3_ctrl_default 0x00000000 479 #define regk_bif_dma_rw_ch3_start_default 0x00000000 480 #define regk_bif_dma_rw_intr_mask_default 0x00000000 481 #define regk_bif_dma_rw_pin0_cfg_default 0x00000000 482 #define regk_bif_dma_rw_pin1_cfg_default 0x00000000 483 #define regk_bif_dma_rw_pin2_cfg_default 0x00000000 484 #define regk_bif_dma_rw_pin3_cfg_default 0x00000000 485 #define regk_bif_dma_rw_pin4_cfg_default 0x00000000 486 #define regk_bif_dma_rw_pin5_cfg_default 0x00000000 487 #define regk_bif_dma_rw_pin6_cfg_default 0x00000000 488 #define regk_bif_dma_rw_pin7_cfg_default 0x00000000 489 #define regk_bif_dma_slave 0x00000002 490 #define regk_bif_dma_sreq 0x00000006 491 #define regk_bif_dma_sreq_inv 0x00000007 492 #define regk_bif_dma_tc 0x00000004 493 #define regk_bif_dma_tc_inv 0x00000005 494 #define regk_bif_dma_yes 0x00000001 495 #endif /* __bif_dma_defs_asm_h */ 496