Searched refs:ref_divider (Results 1 – 9 of 9) sorted by relevance
31 u32 ref_divider; member
134 frequency += config->ref_divider >> 1; in tda665x_set_state()135 frequency /= config->ref_divider; in tda665x_set_state()
49 .ref_divider = 100000, /* 1/6 MHz */
370 u32 ref_divider; member877 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); in aty128_get_pllinfo()882 par->constants.xclk, par->constants.ref_divider, in aty128_get_pllinfo()938 par->constants.ref_divider = in aty128_timings()942 if (!par->constants.ref_divider) { in aty128_timings()943 par->constants.ref_divider = 0x3b; in aty128_timings()948 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); in aty128_timings()1300 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); in aty128_set_pll()1354 n = c.ref_divider * output_freq; in aty128_var_to_pll()1363 c.ref_divider, period_in_ps); in aty128_var_to_pll()
198 rinfo->panel_info.ref_divider = BIOS_IN16(tmp + 46); in radeon_get_panel_info_BIOS()201 if (rinfo->panel_info.ref_divider != 0 && in radeon_get_panel_info_BIOS()205 pr_debug("ref_divider = %x\n", rinfo->panel_info.ref_divider); in radeon_get_panel_info_BIOS()668 rinfo->panel_info.ref_divider = rinfo->pll.ref_div; in radeon_fixup_panel_info()
61 u16 ref_divider; member
263 int ref_divider; member
3424 pll_block.ref_freq, pll_block.ref_divider); in init_from_bios()3432 par->pll_limits.ref_div = pll_block.ref_divider; in init_from_bios()
1597 newmode->ppll_ref_div = rinfo->panel_info.ref_divider; in radeonfb_set_par()