1 /* 2 * SDVO command definitions and structures. 3 * 4 * Copyright (c) 2008, Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Authors: 20 * Eric Anholt <eric@anholt.net> 21 */ 22 23 #define SDVO_OUTPUT_FIRST (0) 24 #define SDVO_OUTPUT_TMDS0 (1 << 0) 25 #define SDVO_OUTPUT_RGB0 (1 << 1) 26 #define SDVO_OUTPUT_CVBS0 (1 << 2) 27 #define SDVO_OUTPUT_SVID0 (1 << 3) 28 #define SDVO_OUTPUT_YPRPB0 (1 << 4) 29 #define SDVO_OUTPUT_SCART0 (1 << 5) 30 #define SDVO_OUTPUT_LVDS0 (1 << 6) 31 #define SDVO_OUTPUT_TMDS1 (1 << 8) 32 #define SDVO_OUTPUT_RGB1 (1 << 9) 33 #define SDVO_OUTPUT_CVBS1 (1 << 10) 34 #define SDVO_OUTPUT_SVID1 (1 << 11) 35 #define SDVO_OUTPUT_YPRPB1 (1 << 12) 36 #define SDVO_OUTPUT_SCART1 (1 << 13) 37 #define SDVO_OUTPUT_LVDS1 (1 << 14) 38 #define SDVO_OUTPUT_LAST (14) 39 40 struct psb_intel_sdvo_caps { 41 u8 vendor_id; 42 u8 device_id; 43 u8 device_rev_id; 44 u8 sdvo_version_major; 45 u8 sdvo_version_minor; 46 unsigned int sdvo_inputs_mask:2; 47 unsigned int smooth_scaling:1; 48 unsigned int sharp_scaling:1; 49 unsigned int up_scaling:1; 50 unsigned int down_scaling:1; 51 unsigned int stall_support:1; 52 unsigned int pad:1; 53 u16 output_flags; 54 } __attribute__ ((packed)); 55 56 /** This matches the EDID DTD structure, more or less */ 57 struct psb_intel_sdvo_dtd { 58 struct { 59 u16 clock; /**< pixel clock, in 10kHz units */ 60 u8 h_active; /**< lower 8 bits (pixels) */ 61 u8 h_blank; /**< lower 8 bits (pixels) */ 62 u8 h_high; /**< upper 4 bits each h_active, h_blank */ 63 u8 v_active; /**< lower 8 bits (lines) */ 64 u8 v_blank; /**< lower 8 bits (lines) */ 65 u8 v_high; /**< upper 4 bits each v_active, v_blank */ 66 } part1; 67 68 struct { 69 u8 h_sync_off; 70 /**< lower 8 bits, from hblank start */ 71 u8 h_sync_width;/**< lower 8 bits (pixels) */ 72 /** lower 4 bits each vsync offset, vsync width */ 73 u8 v_sync_off_width; 74 /** 75 * 2 high bits of hsync offset, 2 high bits of hsync width, 76 * bits 4-5 of vsync offset, and 2 high bits of vsync width. 77 */ 78 u8 sync_off_width_high; 79 u8 dtd_flags; 80 u8 sdvo_flags; 81 /** bits 6-7 of vsync offset at bits 6-7 */ 82 u8 v_sync_off_high; 83 u8 reserved; 84 } part2; 85 } __attribute__ ((packed)); 86 87 struct psb_intel_sdvo_pixel_clock_range { 88 u16 min; /**< pixel clock, in 10kHz units */ 89 u16 max; /**< pixel clock, in 10kHz units */ 90 } __attribute__ ((packed)); 91 92 struct psb_intel_sdvo_preferred_input_timing_args { 93 u16 clock; 94 u16 width; 95 u16 height; 96 } __attribute__ ((packed)); 97 98 /* I2C registers for SDVO */ 99 #define SDVO_I2C_ARG_0 0x07 100 #define SDVO_I2C_ARG_1 0x06 101 #define SDVO_I2C_ARG_2 0x05 102 #define SDVO_I2C_ARG_3 0x04 103 #define SDVO_I2C_ARG_4 0x03 104 #define SDVO_I2C_ARG_5 0x02 105 #define SDVO_I2C_ARG_6 0x01 106 #define SDVO_I2C_ARG_7 0x00 107 #define SDVO_I2C_OPCODE 0x08 108 #define SDVO_I2C_CMD_STATUS 0x09 109 #define SDVO_I2C_RETURN_0 0x0a 110 #define SDVO_I2C_RETURN_1 0x0b 111 #define SDVO_I2C_RETURN_2 0x0c 112 #define SDVO_I2C_RETURN_3 0x0d 113 #define SDVO_I2C_RETURN_4 0x0e 114 #define SDVO_I2C_RETURN_5 0x0f 115 #define SDVO_I2C_RETURN_6 0x10 116 #define SDVO_I2C_RETURN_7 0x11 117 #define SDVO_I2C_VENDOR_BEGIN 0x20 118 119 /* Status results */ 120 #define SDVO_CMD_STATUS_POWER_ON 0x0 121 #define SDVO_CMD_STATUS_SUCCESS 0x1 122 #define SDVO_CMD_STATUS_NOTSUPP 0x2 123 #define SDVO_CMD_STATUS_INVALID_ARG 0x3 124 #define SDVO_CMD_STATUS_PENDING 0x4 125 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5 126 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6 127 128 /* SDVO commands, argument/result registers */ 129 130 #define SDVO_CMD_RESET 0x01 131 132 /** Returns a struct psb_intel_sdvo_caps */ 133 #define SDVO_CMD_GET_DEVICE_CAPS 0x02 134 135 #define SDVO_CMD_GET_FIRMWARE_REV 0x86 136 # define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0 137 # define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1 138 # define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2 139 140 /** 141 * Reports which inputs are trained (managed to sync). 142 * 143 * Devices must have trained within 2 vsyncs of a mode change. 144 */ 145 #define SDVO_CMD_GET_TRAINED_INPUTS 0x03 146 struct psb_intel_sdvo_get_trained_inputs_response { 147 unsigned int input0_trained:1; 148 unsigned int input1_trained:1; 149 unsigned int pad:6; 150 } __attribute__ ((packed)); 151 152 /** Returns a struct psb_intel_sdvo_output_flags of active outputs. */ 153 #define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04 154 155 /** 156 * Sets the current set of active outputs. 157 * 158 * Takes a struct psb_intel_sdvo_output_flags. 159 * Must be preceded by a SET_IN_OUT_MAP 160 * on multi-output devices. 161 */ 162 #define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05 163 164 /** 165 * Returns the current mapping of SDVO inputs to outputs on the device. 166 * 167 * Returns two struct psb_intel_sdvo_output_flags structures. 168 */ 169 #define SDVO_CMD_GET_IN_OUT_MAP 0x06 170 171 /** 172 * Sets the current mapping of SDVO inputs to outputs on the device. 173 * 174 * Takes two struct i380_sdvo_output_flags structures. 175 */ 176 #define SDVO_CMD_SET_IN_OUT_MAP 0x07 177 178 /** 179 * Returns a struct psb_intel_sdvo_output_flags of attached displays. 180 */ 181 #define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b 182 183 /** 184 * Returns a struct psb_intel_sdvo_ouptut_flags of displays supporting hot plugging. 185 */ 186 #define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c 187 188 /** 189 * Takes a struct psb_intel_sdvo_output_flags. 190 */ 191 #define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d 192 193 /** 194 * Returns a struct psb_intel_sdvo_output_flags of displays with hot plug 195 * interrupts enabled. 196 */ 197 #define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e 198 199 #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f 200 struct psb_intel_sdvo_get_interrupt_event_source_response { 201 u16 interrupt_status; 202 unsigned int ambient_light_interrupt:1; 203 unsigned int pad:7; 204 } __attribute__ ((packed)); 205 206 /** 207 * Selects which input is affected by future input commands. 208 * 209 * Commands affected include SET_INPUT_TIMINGS_PART[12], 210 * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12], 211 * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS. 212 */ 213 #define SDVO_CMD_SET_TARGET_INPUT 0x10 214 struct psb_intel_sdvo_set_target_input_args { 215 unsigned int target_1:1; 216 unsigned int pad:7; 217 } __attribute__ ((packed)); 218 219 /** 220 * Takes a struct psb_intel_sdvo_output_flags of which outputs are targeted by 221 * future output commands. 222 * 223 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], 224 * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE. 225 */ 226 #define SDVO_CMD_SET_TARGET_OUTPUT 0x11 227 228 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12 229 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13 230 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14 231 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15 232 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16 233 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17 234 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18 235 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19 236 /* Part 1 */ 237 # define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0 238 # define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1 239 # define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2 240 # define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3 241 # define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4 242 # define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5 243 # define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6 244 # define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7 245 /* Part 2 */ 246 # define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0 247 # define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1 248 # define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2 249 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3 250 # define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4 251 # define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7) 252 # define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5) 253 # define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3) 254 # define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1) 255 # define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5 256 # define SDVO_DTD_SDVO_FLAG_STALL (1 << 7) 257 # define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6) 258 # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6) 259 # define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4) 260 # define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4) 261 # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4) 262 # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4) 263 # define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6 264 265 /** 266 * Generates a DTD based on the given width, height, and flags. 267 * 268 * This will be supported by any device supporting scaling or interlaced 269 * modes. 270 */ 271 #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a 272 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0 273 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1 274 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2 275 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3 276 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4 277 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5 278 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6 279 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0) 280 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1) 281 282 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b 283 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c 284 285 /** Returns a struct psb_intel_sdvo_pixel_clock_range */ 286 #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d 287 /** Returns a struct psb_intel_sdvo_pixel_clock_range */ 288 #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e 289 290 /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ 291 #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f 292 293 /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 294 #define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20 295 /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 296 #define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21 297 # define SDVO_CLOCK_RATE_MULT_1X (1 << 0) 298 # define SDVO_CLOCK_RATE_MULT_2X (1 << 1) 299 # define SDVO_CLOCK_RATE_MULT_4X (1 << 3) 300 301 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 302 303 #define SDVO_CMD_GET_TV_FORMAT 0x28 304 305 #define SDVO_CMD_SET_TV_FORMAT 0x29 306 307 #define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a 308 #define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b 309 #define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c 310 # define SDVO_ENCODER_STATE_ON (1 << 0) 311 # define SDVO_ENCODER_STATE_STANDBY (1 << 1) 312 # define SDVO_ENCODER_STATE_SUSPEND (1 << 2) 313 # define SDVO_ENCODER_STATE_OFF (1 << 3) 314 315 #define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT 0x93 316 317 #define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a 318 # define SDVO_CONTROL_BUS_PROM 0x0 319 # define SDVO_CONTROL_BUS_DDC1 0x1 320 # define SDVO_CONTROL_BUS_DDC2 0x2 321 # define SDVO_CONTROL_BUS_DDC3 0x3 322 323 /* SDVO Bus & SDVO Inputs wiring details*/ 324 /* Bit 0: Is SDVOB connected to In0 (1 = yes, 0 = no*/ 325 /* Bit 1: Is SDVOB connected to In1 (1 = yes, 0 = no*/ 326 /* Bit 2: Is SDVOC connected to In0 (1 = yes, 0 = no*/ 327 /* Bit 3: Is SDVOC connected to In1 (1 = yes, 0 = no*/ 328 #define SDVOB_IN0 0x01 329 #define SDVOB_IN1 0x02 330 #define SDVOC_IN0 0x04 331 #define SDVOC_IN1 0x08 332 333 #define SDVO_DEVICE_NONE 0x00 334 #define SDVO_DEVICE_CRT 0x01 335 #define SDVO_DEVICE_TV 0x02 336 #define SDVO_DEVICE_LVDS 0x04 337 #define SDVO_DEVICE_TMDS 0x08 338 339