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Searched refs:mstp_clks (Results 1 – 13 of 13) sorted by relevance

/linux-2.6.39/arch/sh/kernel/cpu/sh4a/
Dclock-sh7724.c198 static struct clk mstp_clks[HWBLK_NR] = { variable
280 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
281 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
282 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
283 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
284 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
285 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
286 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
287 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
288 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
[all …]
Dclock-sh7723.c150 static struct clk mstp_clks[] = { variable
227 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
228 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
229 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
230 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
231 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
232 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
233 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
234 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
235 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
[all …]
Dclock-sh7786.c93 static struct clk mstp_clks[MSTP_NR] = { variable
148 .clk = &mstp_clks[MSTP029],
153 .clk = &mstp_clks[MSTP028],
158 .clk = &mstp_clks[MSTP027],
163 .clk = &mstp_clks[MSTP026],
168 .clk = &mstp_clks[MSTP025],
173 .clk = &mstp_clks[MSTP024],
175 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
176 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
177 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
[all …]
Dclock-sh7343.c150 static struct clk mstp_clks[MSTP_NR] = { variable
220 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
221 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
222 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
223 CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
224 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
225 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
226 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
227 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
228 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
[all …]
Dclock-sh7366.c152 static struct clk mstp_clks[MSTP_NR] = { variable
218 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
219 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
220 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
221 CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
222 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
223 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
224 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
225 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
226 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
[all …]
Dclock-sh7785.c92 static struct clk mstp_clks[MSTP_NR] = { variable
141 .clk = &mstp_clks[MSTP029],
146 .clk = &mstp_clks[MSTP028],
151 .clk = &mstp_clks[MSTP027],
156 .clk = &mstp_clks[MSTP026],
161 .clk = &mstp_clks[MSTP025],
166 .clk = &mstp_clks[MSTP024],
168 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
169 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
170 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
[all …]
Dclock-sh7722.c150 static struct clk mstp_clks[HWBLK_NR] = { variable
202 CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
203 CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
208 .clk = &mstp_clks[HWBLK_TMU],
213 .clk = &mstp_clks[HWBLK_TMU],
218 .clk = &mstp_clks[HWBLK_TMU],
220 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
221 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
222 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
227 .clk = &mstp_clks[HWBLK_SCIF0],
[all …]
Dclock-shx3.c84 static struct clk mstp_clks[MSTP_NR] = { variable
123 .clk = &mstp_clks[MSTP027],
128 .clk = &mstp_clks[MSTP026],
133 .clk = &mstp_clks[MSTP025],
138 .clk = &mstp_clks[MSTP024],
140 CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
141 CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
142 CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
143 CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
148 .clk = &mstp_clks[MSTP008],
[all …]
Dclock-sh7757.c86 static struct clk mstp_clks[MSTP_NR] = { variable
117 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]),
118 CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]),
123 .clk = &mstp_clks[MSTP113],
128 .clk = &mstp_clks[MSTP114],
134 .clk = &mstp_clks[MSTP112],
139 .clk = &mstp_clks[MSTP111],
144 .clk = &mstp_clks[MSTP110],
146 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
147 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
[all …]
/linux-2.6.39/arch/arm/mach-shmobile/
Dclock-sh7367.c231 static struct clk mstp_clks[MSTP_NR] = { variable
305 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
306 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
307 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
308 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
309 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
310 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
311 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
312 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
313 CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
[all …]
Dclock-sh7377.c242 static struct clk mstp_clks[] = { variable
318 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
319 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
320 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
321 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
322 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
323 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
324 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
325 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
326 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
[all …]
Dclock-sh73a0.c276 static struct clk mstp_clks[MSTP_NR] = { variable
322 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
323 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
324 CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
325 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
326 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
327 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
328 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
329 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
330 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
[all …]
Dclock-sh7372.c518 static struct clk mstp_clks[MSTP_NR] = { variable
608 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
609 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
610 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
611 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
612 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
613 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
614 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
615 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
616 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
[all …]