1 /*****************************************************************************
2  *                                                                           *
3  * File: suni1x10gexp_regs.h                                                 *
4  * $Revision: 1.9 $                                                          *
5  * $Date: 2005/06/22 00:17:04 $                                              *
6  * Description:                                                              *
7  *  PMC/SIERRA (pm3393) MAC-PHY functionality.                               *
8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
9  *                                                                           *
10  * This program is free software; you can redistribute it and/or modify      *
11  * it under the terms of the GNU General Public License, version 2, as       *
12  * published by the Free Software Foundation.                                *
13  *                                                                           *
14  * You should have received a copy of the GNU General Public License along   *
15  * with this program; if not, write to the Free Software Foundation, Inc.,   *
16  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
17  *                                                                           *
18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
19  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
21  *                                                                           *
22  * http://www.chelsio.com                                                    *
23  *                                                                           *
24  * Maintainers: maintainers@chelsio.com                                      *
25  *                                                                           *
26  * Authors: PMC/SIERRA                                                       *
27  *                                                                           *
28  * History:                                                                  *
29  *                                                                           *
30  ****************************************************************************/
31 
32 #ifndef _CXGB_SUNI1x10GEXP_REGS_H_
33 #define _CXGB_SUNI1x10GEXP_REGS_H_
34 
35 /*
36 ** Space allocated for each Exact Match Filter
37 **     There are 8 filter configurations
38 */
39 #define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003
40 
41 #define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)       ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER )
42 
43 /*
44 ** Space allocated for VLAN-Id Filter
45 **      There are 8 filter configurations
46 */
47 #define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001
48 
49 #define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId)   ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER )
50 
51 /*
52 ** Space allocated for each MSTAT Counter
53 */
54 #define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004
55 
56 #define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)       ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT )
57 
58 
59 /******************************************************************************/
60 /** S/UNI-1x10GE-XP REGISTER ADDRESS MAP                                     **/
61 /******************************************************************************/
62 /* Refer to the Register Bit Masks bellow for the naming of each register and */
63 /* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit        */
64 /******************************************************************************/
65 
66 
67 #define SUNI1x10GEXP_REG_IDENTIFICATION                                  0x0000
68 #define SUNI1x10GEXP_REG_PRODUCT_REVISION                                0x0001
69 #define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL                        0x0002
70 #define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL                              0x0003
71 #define SUNI1x10GEXP_REG_DEVICE_STATUS                                   0x0004
72 #define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE               0x0005
73 
74 #define SUNI1x10GEXP_REG_MDIO_COMMAND                                    0x0006
75 #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE                           0x0007
76 #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS                           0x0008
77 #define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS                                 0x0009
78 #define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA                        0x000A
79 #define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA                           0x000B
80 
81 #define SUNI1x10GEXP_REG_OAM_INTF_CTRL                                   0x000C
82 #define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS                         0x000D
83 #define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE                         0x000E
84 #define SUNI1x10GEXP_REG_FREE                                            0x000F
85 
86 #define SUNI1x10GEXP_REG_XTEF_MISC_CTRL                                  0x0010
87 #define SUNI1x10GEXP_REG_XRF_MISC_CTRL                                   0x0011
88 
89 #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1                            0x0100
90 #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2                            0x0101
91 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE                    0x0102
92 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE                   0x0103
93 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS                    0x0104
94 #define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG                         0x0107
95 
96 #define SUNI1x10GEXP_REG_RXXG_CONFIG_1                                   0x2040
97 #define SUNI1x10GEXP_REG_RXXG_CONFIG_2                                   0x2041
98 #define SUNI1x10GEXP_REG_RXXG_CONFIG_3                                   0x2042
99 #define SUNI1x10GEXP_REG_RXXG_INTERRUPT                                  0x2043
100 #define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH                           0x2045
101 #define SUNI1x10GEXP_REG_RXXG_SA_15_0                                    0x2046
102 #define SUNI1x10GEXP_REG_RXXG_SA_31_16                                   0x2047
103 #define SUNI1x10GEXP_REG_RXXG_SA_47_32                                   0x2048
104 #define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD                     0x2049
105 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
106 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
107 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
108 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId)      (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId))
109 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW                     0x204A
110 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID                     0x204B
111 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH                    0x204C
112 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW                     0x204D
113 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID                     0x204E
114 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH                    0x204F
115 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW                     0x2050
116 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID                     0x2051
117 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH                    0x2052
118 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW                     0x2053
119 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID                     0x2054
120 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH                    0x2055
121 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW                     0x2056
122 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID                     0x2057
123 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH                    0x2058
124 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW                     0x2059
125 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID                     0x205A
126 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH                    0x205B
127 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW                     0x205C
128 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID                     0x205D
129 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH                    0x205E
130 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW                     0x205F
131 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID                     0x2060
132 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH                    0x2061
133 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0                          0x2062
134 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1                          0x2063
135 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2                          0x2064
136 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3                          0x2065
137 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4                          0x2066
138 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5                          0x2067
139 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6                          0x2068
140 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7                          0x2069
141 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW                         0x206A
142 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW                      0x206B
143 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH                     0x206C
144 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH                        0x206D
145 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0                   0x206E
146 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1                   0x206F
147 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2                   0x2070
148 
149 #define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL                            0x2081
150 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0                       0x2084
151 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1                       0x2085
152 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2                       0x2086
153 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3                       0x2087
154 #define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE                            0x2088
155 #define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS                            0x2089
156 #define SUNI1x10GEXP_REG_XRF_ERR_STATUS                                  0x208A
157 #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE                       0x208B
158 #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS                       0x208C
159 #define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES                              0x2092
160 
161 #define SUNI1x10GEXP_REG_RXOAM_CONFIG                                    0x20C0
162 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG                           0x20C1
163 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG                           0x20C2
164 #define SUNI1x10GEXP_REG_RXOAM_CONFIG_2                                  0x20C3
165 #define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG                                0x20C4
166 #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES                             0x20C5
167 #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE                          0x20C7
168 #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS                          0x20C8
169 #define SUNI1x10GEXP_REG_RXOAM_STATUS                                    0x20C9
170 #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT                             0x20CA
171 #define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT                       0x20CB
172 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB                 0x20CC
173 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB                 0x20CD
174 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB               0x20CE
175 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB               0x20CF
176 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB               0x20D0
177 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB               0x20D1
178 #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB                     0x20D2
179 #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB                     0x20D3
180 #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB                     0x20D4
181 #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB                     0x20D5
182 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB                 0x20D6
183 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB                 0x20D7
184 
185 #define SUNI1x10GEXP_REG_MSTAT_CONTROL                                   0x2100
186 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0                        0x2101
187 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1                        0x2102
188 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2                        0x2103
189 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3                        0x2104
190 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0                          0x2105
191 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1                          0x2106
192 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2                          0x2107
193 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3                          0x2108
194 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS                     0x2109
195 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW                    0x210A
196 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE                 0x210B
197 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH                   0x210C
198 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId)   (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
199 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId)   (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
200 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId)  (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
201 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW                             0x2110
202 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID                             0x2111
203 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH                            0x2112
204 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD                           0x2113
205 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW                             0x2114
206 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID                             0x2115
207 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH                            0x2116
208 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD                           0x2117
209 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW                             0x2118
210 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID                             0x2119
211 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH                            0x211A
212 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD                           0x211B
213 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW                             0x211C
214 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID                             0x211D
215 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH                            0x211E
216 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD                           0x211F
217 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW                             0x2120
218 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID                             0x2121
219 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH                            0x2122
220 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD                           0x2123
221 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW                             0x2124
222 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID                             0x2125
223 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH                            0x2126
224 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD                           0x2127
225 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW                             0x2128
226 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID                             0x2129
227 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH                            0x212A
228 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD                           0x212B
229 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW                             0x212C
230 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID                             0x212D
231 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH                            0x212E
232 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD                           0x212F
233 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW                             0x2130
234 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID                             0x2131
235 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH                            0x2132
236 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD                           0x2133
237 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW                             0x2134
238 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID                             0x2135
239 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH                            0x2136
240 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD                           0x2137
241 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW                            0x2138
242 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID                            0x2139
243 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH                           0x213A
244 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD                          0x213B
245 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW                            0x213C
246 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID                            0x213D
247 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH                           0x213E
248 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD                          0x213F
249 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW                            0x2140
250 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID                            0x2141
251 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH                           0x2142
252 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD                          0x2143
253 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW                            0x2144
254 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID                            0x2145
255 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH                           0x2146
256 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD                          0x2147
257 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW                            0x2148
258 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID                            0x2149
259 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH                           0x214A
260 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD                          0x214B
261 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW                            0x214C
262 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID                            0x214D
263 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH                           0x214E
264 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD                          0x214F
265 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW                            0x2150
266 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID                            0x2151
267 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH                           0x2152
268 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD                          0x2153
269 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW                            0x2154
270 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID                            0x2155
271 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH                           0x2156
272 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD                          0x2157
273 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW                            0x2158
274 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID                            0x2159
275 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH                           0x215A
276 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD                          0x215B
277 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW                            0x215C
278 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID                            0x215D
279 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH                           0x215E
280 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD                          0x215F
281 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW                            0x2160
282 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID                            0x2161
283 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH                           0x2162
284 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD                          0x2163
285 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW                            0x2164
286 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID                            0x2165
287 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH                           0x2166
288 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD                          0x2167
289 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW                            0x2168
290 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID                            0x2169
291 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH                           0x216A
292 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD                          0x216B
293 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW                            0x216C
294 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID                            0x216D
295 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH                           0x216E
296 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD                          0x216F
297 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW                            0x2170
298 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID                            0x2171
299 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH                           0x2172
300 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD                          0x2173
301 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW                            0x2174
302 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID                            0x2175
303 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH                           0x2176
304 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD                          0x2177
305 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW                            0x2178
306 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID                            0x2179
307 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH                           0x217a
308 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD                          0x217b
309 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW                            0x217c
310 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID                            0x217d
311 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH                           0x217e
312 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD                          0x217f
313 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW                            0x2180
314 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID                            0x2181
315 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH                           0x2182
316 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD                          0x2183
317 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW                            0x2184
318 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID                            0x2185
319 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH                           0x2186
320 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD                          0x2187
321 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW                            0x2188
322 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID                            0x2189
323 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH                           0x218A
324 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD                          0x218B
325 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW                            0x218C
326 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID                            0x218D
327 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH                           0x218E
328 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD                          0x218F
329 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW                            0x2190
330 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID                            0x2191
331 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH                           0x2192
332 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD                          0x2193
333 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW                            0x2194
334 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID                            0x2195
335 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH                           0x2196
336 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD                          0x2197
337 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW                            0x2198
338 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID                            0x2199
339 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH                           0x219A
340 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD                          0x219B
341 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW                            0x219C
342 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID                            0x219D
343 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH                           0x219E
344 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD                          0x219F
345 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW                            0x21A0
346 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID                            0x21A1
347 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH                           0x21A2
348 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD                          0x21A3
349 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW                            0x21A4
350 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID                            0x21A5
351 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH                           0x21A6
352 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD                          0x21A7
353 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW                            0x21A8
354 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID                            0x21A9
355 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH                           0x21AA
356 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD                          0x21AB
357 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW                            0x21AC
358 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID                            0x21AD
359 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH                           0x21AE
360 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD                          0x21AF
361 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW                            0x21B0
362 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID                            0x21B1
363 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH                           0x21B2
364 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD                          0x21B3
365 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW                            0x21B4
366 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID                            0x21B5
367 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH                           0x21B6
368 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD                          0x21B7
369 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW                            0x21B8
370 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID                            0x21B9
371 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH                           0x21BA
372 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD                          0x21BB
373 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW                            0x21BC
374 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID                            0x21BD
375 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH                           0x21BE
376 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD                          0x21BF
377 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW                            0x21C0
378 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID                            0x21C1
379 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH                           0x21C2
380 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD                          0x21C3
381 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW                            0x21C4
382 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID                            0x21C5
383 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH                           0x21C6
384 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD                          0x21C7
385 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW                            0x21C8
386 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID                            0x21C9
387 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH                           0x21CA
388 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD                          0x21CB
389 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW                            0x21CC
390 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID                            0x21CD
391 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH                           0x21CE
392 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD                          0x21CF
393 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW                            0x21D0
394 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID                            0x21D1
395 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH                           0x21D2
396 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD                          0x21D3
397 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW                            0x21D4
398 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID                            0x21D5
399 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH                           0x21D6
400 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD                          0x21D7
401 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW                            0x21D8
402 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID                            0x21D9
403 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH                           0x21DA
404 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD                          0x21DB
405 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW                            0x21DC
406 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID                            0x21DD
407 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH                           0x21DE
408 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD                          0x21DF
409 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW                            0x21E0
410 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID                            0x21E1
411 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH                           0x21E2
412 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD                          0x21E3
413 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW                            0x21E4
414 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID                            0x21E5
415 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH                           0x21E6
416 #define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM                               51
417 
418 #define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG                              0x2200
419 #define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION                          0x2201
420 #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE                       0x2209
421 #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT                    0x220A
422 #define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS                      0x220D
423 #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION     0x220E
424 #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT              0x220F
425 #define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT        0x2210
426 #define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT      0x2211
427 
428 #define SUNI1x10GEXP_REG_PL4MOS_CONFIG                                   0x2240
429 #define SUNI1x10GEXP_REG_PL4MOS_MASK                                     0x2241
430 #define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING                         0x2242
431 #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1                                0x2243
432 #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2                                0x2244
433 #define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE                            0x2245
434 
435 #define SUNI1x10GEXP_REG_PL4ODP_CONFIG                                   0x2280
436 #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK                           0x2282
437 #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT                                0x2283
438 #define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T                             0x2284
439 
440 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS                        0x2300
441 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE                        0x2301
442 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK                          0x2302
443 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS                        0x2303
444 #define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS                      0x2304
445 #define SUNI1x10GEXP_REG_PL4IO_CONFIG                                    0x2305
446 
447 #define SUNI1x10GEXP_REG_TXXG_CONFIG_1                                   0x3040
448 #define SUNI1x10GEXP_REG_TXXG_CONFIG_2                                   0x3041
449 #define SUNI1x10GEXP_REG_TXXG_CONFIG_3                                   0x3042
450 #define SUNI1x10GEXP_REG_TXXG_INTERRUPT                                  0x3043
451 #define SUNI1x10GEXP_REG_TXXG_STATUS                                     0x3044
452 #define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE                             0x3045
453 #define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE                             0x3046
454 #define SUNI1x10GEXP_REG_TXXG_SA_15_0                                    0x3047
455 #define SUNI1x10GEXP_REG_TXXG_SA_31_16                                   0x3048
456 #define SUNI1x10GEXP_REG_TXXG_SA_47_32                                   0x3049
457 #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER                                0x304D
458 #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL                       0x304E
459 #define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER                       0x3051
460 #define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG                       0x3052
461 
462 #define SUNI1x10GEXP_REG_XTEF_CTRL                                       0x3080
463 #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS                           0x3084
464 #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE                           0x3085
465 #define SUNI1x10GEXP_REG_XTEF_VISIBILITY                                 0x3086
466 
467 #define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG                                0x30C0
468 #define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG                          0x30C1
469 #define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG                      0x30C2
470 #define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES                        0x30C3
471 #define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES                        0x30C4
472 #define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES                        0x30C5
473 #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE                          0x30C6
474 #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS                          0x30C7
475 #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB                          0x30C8
476 #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB                          0x30C9
477 #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB                        0x30CA
478 #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB                        0x30CB
479 #define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK                            0x30CC
480 #define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK                            0x30CD
481 #define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK                            0x30CE
482 #define SUNI1x10GEXP_REG_TXOAM_COSET                                     0x30CF
483 #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB                 0x30D0
484 #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB                 0x30D1
485 #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB               0x30D2
486 #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB               0x30D3
487 
488 
489 #define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG                              0x3200
490 #define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS                         0x3201
491 #define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS                      0x3202
492 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT                       0x3203
493 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT                      0x3204
494 #define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT    0x3205
495 #define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT  0x3206
496 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD           0x3207
497 #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE                 0x320C
498 #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION             0x320D
499 #define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION                          0x3210
500 
501 #define SUNI1x10GEXP_REG_PL4IDU_CONFIG                                   0x3280
502 #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK                           0x3282
503 #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT                                0x3283
504 
505 
506 /*----------------------------------------*/
507 #define SUNI1x10GEXP_REG_MAX_OFFSET                                      0x3480
508 
509 /******************************************************************************/
510 /*                 -- End register offset definitions --                      */
511 /******************************************************************************/
512 
513 /******************************************************************************/
514 /** SUNI-1x10GE-XP REGISTER BIT MASKS                                        **/
515 /******************************************************************************/
516 
517 #define SUNI1x10GEXP_BITMSK_BITS_1   0x00001
518 #define SUNI1x10GEXP_BITMSK_BITS_2   0x00003
519 #define SUNI1x10GEXP_BITMSK_BITS_3   0x00007
520 #define SUNI1x10GEXP_BITMSK_BITS_4   0x0000f
521 #define SUNI1x10GEXP_BITMSK_BITS_5   0x0001f
522 #define SUNI1x10GEXP_BITMSK_BITS_6   0x0003f
523 #define SUNI1x10GEXP_BITMSK_BITS_7   0x0007f
524 #define SUNI1x10GEXP_BITMSK_BITS_8   0x000ff
525 #define SUNI1x10GEXP_BITMSK_BITS_9   0x001ff
526 #define SUNI1x10GEXP_BITMSK_BITS_10  0x003ff
527 #define SUNI1x10GEXP_BITMSK_BITS_11  0x007ff
528 #define SUNI1x10GEXP_BITMSK_BITS_12  0x00fff
529 #define SUNI1x10GEXP_BITMSK_BITS_13  0x01fff
530 #define SUNI1x10GEXP_BITMSK_BITS_14  0x03fff
531 #define SUNI1x10GEXP_BITMSK_BITS_15  0x07fff
532 #define SUNI1x10GEXP_BITMSK_BITS_16  0x0ffff
533 
534 #define mSUNI1x10GEXP_CLR_MSBITS_1(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_15)
535 #define mSUNI1x10GEXP_CLR_MSBITS_2(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_14)
536 #define mSUNI1x10GEXP_CLR_MSBITS_3(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_13)
537 #define mSUNI1x10GEXP_CLR_MSBITS_4(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_12)
538 #define mSUNI1x10GEXP_CLR_MSBITS_5(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_11)
539 #define mSUNI1x10GEXP_CLR_MSBITS_6(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_10)
540 #define mSUNI1x10GEXP_CLR_MSBITS_7(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_9)
541 #define mSUNI1x10GEXP_CLR_MSBITS_8(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_8)
542 #define mSUNI1x10GEXP_CLR_MSBITS_9(v)  ((v) & SUNI1x10GEXP_BITMSK_BITS_7)
543 #define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6)
544 #define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5)
545 #define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4)
546 #define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3)
547 #define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2)
548 #define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1)
549 
550 #define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0)
551 
552 
553 
554 /*----------------------------------------------------------------------------
555  * Register 0x0001: S/UNI-1x10GE-XP Product Revision
556  *    Bit 3-0  REVISION
557  *----------------------------------------------------------------------------*/
558 #define SUNI1x10GEXP_BITMSK_REVISION  0x000F
559 
560 /*----------------------------------------------------------------------------
561  * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control
562  *    Bit 2  XAUI_ARESETB
563  *    Bit 1  PL4_ARESETB
564  *    Bit 0  DRESETB
565  *----------------------------------------------------------------------------*/
566 #define SUNI1x10GEXP_BITMSK_XAUI_ARESET  0x0004
567 #define SUNI1x10GEXP_BITMSK_PL4_ARESET   0x0002
568 #define SUNI1x10GEXP_BITMSK_DRESETB      0x0001
569 
570 /*----------------------------------------------------------------------------
571  * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control
572  *    Bit 11  PL4IO_OUTCLKSEL
573  *    Bit 9   SYSPCSLB
574  *    Bit 8   LINEPCSLB
575  *    Bit 7   MSTAT_BYPASS
576  *    Bit 6   RXXG_BYPASS
577  *    Bit 5   TXXG_BYPASS
578  *    Bit 4   SOP_PAD_EN
579  *    Bit 1   LOS_INV
580  *    Bit 0   OVERRIDE_LOS
581  *----------------------------------------------------------------------------*/
582 #define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL  0x0800
583 #define SUNI1x10GEXP_BITMSK_SYSPCSLB         0x0200
584 #define SUNI1x10GEXP_BITMSK_LINEPCSLB        0x0100
585 #define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS     0x0080
586 #define SUNI1x10GEXP_BITMSK_RXXG_BYPASS      0x0040
587 #define SUNI1x10GEXP_BITMSK_TXXG_BYPASS      0x0020
588 #define SUNI1x10GEXP_BITMSK_SOP_PAD_EN       0x0010
589 #define SUNI1x10GEXP_BITMSK_LOS_INV          0x0002
590 #define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS     0x0001
591 
592 /*----------------------------------------------------------------------------
593  * Register 0x0004: S/UNI-1x10GE-XP Device Status
594  *    Bit 9 TOP_SXRA_EXPIRED
595  *    Bit 8 TOP_MDIO_BUSY
596  *    Bit 7 TOP_DTRB
597  *    Bit 6 TOP_EXPIRED
598  *    Bit 5 TOP_PAUSED
599  *    Bit 4 TOP_PL4_ID_DOOL
600  *    Bit 3 TOP_PL4_IS_DOOL
601  *    Bit 2 TOP_PL4_ID_ROOL
602  *    Bit 1 TOP_PL4_IS_ROOL
603  *    Bit 0 TOP_PL4_OUT_ROOL
604  *----------------------------------------------------------------------------*/
605 #define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED  0x0200
606 #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY     0x0100
607 #define SUNI1x10GEXP_BITMSK_TOP_DTRB          0x0080
608 #define SUNI1x10GEXP_BITMSK_TOP_EXPIRED       0x0040
609 #define SUNI1x10GEXP_BITMSK_TOP_PAUSED        0x0020
610 #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL   0x0010
611 #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL   0x0008
612 #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL   0x0004
613 #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL   0x0002
614 #define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL  0x0001
615 
616 /*----------------------------------------------------------------------------
617  * Register 0x0005: Global Performance Update and Clock Monitors
618  *    Bit 15 TIP
619  *    Bit 8  XAUI_REF_CLKA
620  *    Bit 7  RXLANE3CLKA
621  *    Bit 6  RXLANE2CLKA
622  *    Bit 5  RXLANE1CLKA
623  *    Bit 4  RXLANE0CLKA
624  *    Bit 3  CSUCLKA
625  *    Bit 2  TDCLKA
626  *    Bit 1  RSCLKA
627  *    Bit 0  RDCLKA
628  *----------------------------------------------------------------------------*/
629 #define SUNI1x10GEXP_BITMSK_TIP            0x8000
630 #define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA  0x0100
631 #define SUNI1x10GEXP_BITMSK_RXLANE3CLKA    0x0080
632 #define SUNI1x10GEXP_BITMSK_RXLANE2CLKA    0x0040
633 #define SUNI1x10GEXP_BITMSK_RXLANE1CLKA    0x0020
634 #define SUNI1x10GEXP_BITMSK_RXLANE0CLKA    0x0010
635 #define SUNI1x10GEXP_BITMSK_CSUCLKA        0x0008
636 #define SUNI1x10GEXP_BITMSK_TDCLKA         0x0004
637 #define SUNI1x10GEXP_BITMSK_RSCLKA         0x0002
638 #define SUNI1x10GEXP_BITMSK_RDCLKA         0x0001
639 
640 /*----------------------------------------------------------------------------
641  * Register 0x0006: MDIO Command
642  *    Bit 4 MDIO_RDINC
643  *    Bit 3 MDIO_RSTAT
644  *    Bit 2 MDIO_LCTLD
645  *    Bit 1 MDIO_LCTLA
646  *    Bit 0 MDIO_SPRE
647  *----------------------------------------------------------------------------*/
648 #define SUNI1x10GEXP_BITMSK_MDIO_RDINC  0x0010
649 #define SUNI1x10GEXP_BITMSK_MDIO_RSTAT  0x0008
650 #define SUNI1x10GEXP_BITMSK_MDIO_LCTLD  0x0004
651 #define SUNI1x10GEXP_BITMSK_MDIO_LCTLA  0x0002
652 #define SUNI1x10GEXP_BITMSK_MDIO_SPRE   0x0001
653 
654 /*----------------------------------------------------------------------------
655  * Register 0x0007: MDIO Interrupt Enable
656  *    Bit 0 MDIO_BUSY_EN
657  *----------------------------------------------------------------------------*/
658 #define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN  0x0001
659 
660 /*----------------------------------------------------------------------------
661  * Register 0x0008: MDIO Interrupt Status
662  *    Bit 0 MDIO_BUSYI
663  *----------------------------------------------------------------------------*/
664 #define SUNI1x10GEXP_BITMSK_MDIO_BUSYI  0x0001
665 
666 /*----------------------------------------------------------------------------
667  * Register 0x0009: MMD PHY Address
668  *    Bit 12-8 MDIO_DEVADR
669  *    Bit 4-0 MDIO_PRTADR
670  *----------------------------------------------------------------------------*/
671 #define SUNI1x10GEXP_BITMSK_MDIO_DEVADR  0x1F00
672 #define SUNI1x10GEXP_BITOFF_MDIO_DEVADR  8
673 #define SUNI1x10GEXP_BITMSK_MDIO_PRTADR  0x001F
674 #define SUNI1x10GEXP_BITOFF_MDIO_PRTADR  0
675 
676 /*----------------------------------------------------------------------------
677  * Register 0x000C: OAM Interface Control
678  *    Bit 6 MDO_OD_ENB
679  *    Bit 5 MDI_INV
680  *    Bit 4 MDI_SEL
681  *    Bit 3 RXOAMEN
682  *    Bit 2 RXOAMCLKEN
683  *    Bit 1 TXOAMEN
684  *    Bit 0 TXOAMCLKEN
685  *----------------------------------------------------------------------------*/
686 #define SUNI1x10GEXP_BITMSK_MDO_OD_ENB  0x0040
687 #define SUNI1x10GEXP_BITMSK_MDI_INV     0x0020
688 #define SUNI1x10GEXP_BITMSK_MDI_SEL     0x0010
689 #define SUNI1x10GEXP_BITMSK_RXOAMEN     0x0008
690 #define SUNI1x10GEXP_BITMSK_RXOAMCLKEN  0x0004
691 #define SUNI1x10GEXP_BITMSK_TXOAMEN     0x0002
692 #define SUNI1x10GEXP_BITMSK_TXOAMCLKEN  0x0001
693 
694 /*----------------------------------------------------------------------------
695  * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status
696  *    Bit 15 TOP_PL4IO_INT
697  *    Bit 14 TOP_IRAM_INT
698  *    Bit 13 TOP_ERAM_INT
699  *    Bit 12 TOP_XAUI_INT
700  *    Bit 11 TOP_MSTAT_INT
701  *    Bit 10 TOP_RXXG_INT
702  *    Bit 9 TOP_TXXG_INT
703  *    Bit 8 TOP_XRF_INT
704  *    Bit 7 TOP_XTEF_INT
705  *    Bit 6 TOP_MDIO_BUSY_INT
706  *    Bit 5 TOP_RXOAM_INT
707  *    Bit 4 TOP_TXOAM_INT
708  *    Bit 3 TOP_IFLX_INT
709  *    Bit 2 TOP_EFLX_INT
710  *    Bit 1 TOP_PL4ODP_INT
711  *    Bit 0 TOP_PL4IDU_INT
712  *----------------------------------------------------------------------------*/
713 #define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT      0x8000
714 #define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT       0x4000
715 #define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT       0x2000
716 #define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT       0x1000
717 #define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT      0x0800
718 #define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT       0x0400
719 #define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT       0x0200
720 #define SUNI1x10GEXP_BITMSK_TOP_XRF_INT        0x0100
721 #define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT       0x0080
722 #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT  0x0040
723 #define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT      0x0020
724 #define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT      0x0010
725 #define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT       0x0008
726 #define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT       0x0004
727 #define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT     0x0002
728 #define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT     0x0001
729 
730 /*----------------------------------------------------------------------------
731  * Register 0x000E:PM3393 Global interrupt enable
732  *    Bit 15 TOP_INTE
733  *----------------------------------------------------------------------------*/
734 #define SUNI1x10GEXP_BITMSK_TOP_INTE  0x8000
735 
736 /*----------------------------------------------------------------------------
737  * Register 0x0010: XTEF Miscellaneous Control
738  *    Bit 7 RF_VAL
739  *    Bit 6 RF_OVERRIDE
740  *    Bit 5 LF_VAL
741  *    Bit 4 LF_OVERRIDE
742  *----------------------------------------------------------------------------*/
743 #define SUNI1x10GEXP_BITMSK_RF_VAL             0x0080
744 #define SUNI1x10GEXP_BITMSK_RF_OVERRIDE        0x0040
745 #define SUNI1x10GEXP_BITMSK_LF_VAL             0x0020
746 #define SUNI1x10GEXP_BITMSK_LF_OVERRIDE        0x0010
747 #define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL  0x00F0
748 
749 /*----------------------------------------------------------------------------
750  * Register 0x0011: XRF Miscellaneous Control
751  *    Bit 6-4 EN_IDLE_REP
752  *----------------------------------------------------------------------------*/
753 #define SUNI1x10GEXP_BITMSK_EN_IDLE_REP  0x0070
754 
755 /*----------------------------------------------------------------------------
756  * Register 0x0100: SERDES 3125 Configuration Register 1
757  *    Bit 10 RXEQB_3
758  *    Bit 8  RXEQB_2
759  *    Bit 6  RXEQB_1
760  *    Bit 4  RXEQB_0
761  *----------------------------------------------------------------------------*/
762 #define SUNI1x10GEXP_BITMSK_RXEQB    0x0FF0
763 #define SUNI1x10GEXP_BITOFF_RXEQB_3  10
764 #define SUNI1x10GEXP_BITOFF_RXEQB_2  8
765 #define SUNI1x10GEXP_BITOFF_RXEQB_1  6
766 #define SUNI1x10GEXP_BITOFF_RXEQB_0  4
767 
768 /*----------------------------------------------------------------------------
769  * Register 0x0101: SERDES 3125 Configuration Register 2
770  *    Bit 12 YSEL
771  *    Bit  7 PRE_EMPH_3
772  *    Bit  6 PRE_EMPH_2
773  *    Bit  5 PRE_EMPH_1
774  *    Bit  4 PRE_EMPH_0
775  *----------------------------------------------------------------------------*/
776 #define SUNI1x10GEXP_BITMSK_YSEL        0x1000
777 #define SUNI1x10GEXP_BITMSK_PRE_EMPH    0x00F0
778 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_3  0x0080
779 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_2  0x0040
780 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_1  0x0020
781 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_0  0x0010
782 
783 /*----------------------------------------------------------------------------
784  * Register 0x0102: SERDES 3125 Interrupt Enable Register
785  *    Bit 3 LASIE
786  *    Bit 2 SPLL_RAE
787  *    Bit 1 MPLL_RAE
788  *    Bit 0 PLL_LOCKE
789  *----------------------------------------------------------------------------*/
790 #define SUNI1x10GEXP_BITMSK_LASIE      0x0008
791 #define SUNI1x10GEXP_BITMSK_SPLL_RAE   0x0004
792 #define SUNI1x10GEXP_BITMSK_MPLL_RAE   0x0002
793 #define SUNI1x10GEXP_BITMSK_PLL_LOCKE  0x0001
794 
795 /*----------------------------------------------------------------------------
796  * Register 0x0103: SERDES 3125 Interrupt Visibility Register
797  *    Bit 3 LASIV
798  *    Bit 2 SPLL_RAV
799  *    Bit 1 MPLL_RAV
800  *    Bit 0 PLL_LOCKV
801  *----------------------------------------------------------------------------*/
802 #define SUNI1x10GEXP_BITMSK_LASIV      0x0008
803 #define SUNI1x10GEXP_BITMSK_SPLL_RAV   0x0004
804 #define SUNI1x10GEXP_BITMSK_MPLL_RAV   0x0002
805 #define SUNI1x10GEXP_BITMSK_PLL_LOCKV  0x0001
806 
807 /*----------------------------------------------------------------------------
808  * Register 0x0104: SERDES 3125 Interrupt Status Register
809  *    Bit 3 LASII
810  *    Bit 2 SPLL_RAI
811  *    Bit 1 MPLL_RAI
812  *    Bit 0 PLL_LOCKI
813  *----------------------------------------------------------------------------*/
814 #define SUNI1x10GEXP_BITMSK_LASII      0x0008
815 #define SUNI1x10GEXP_BITMSK_SPLL_RAI   0x0004
816 #define SUNI1x10GEXP_BITMSK_MPLL_RAI   0x0002
817 #define SUNI1x10GEXP_BITMSK_PLL_LOCKI  0x0001
818 
819 /*----------------------------------------------------------------------------
820  * Register 0x0107: SERDES 3125 Test Configuration
821  *    Bit 12 DUALTX
822  *    Bit 10 HC_1
823  *    Bit  9 HC_0
824  *----------------------------------------------------------------------------*/
825 #define SUNI1x10GEXP_BITMSK_DUALTX  0x1000
826 #define SUNI1x10GEXP_BITMSK_HC      0x0600
827 #define SUNI1x10GEXP_BITOFF_HC_0    9
828 
829 /*----------------------------------------------------------------------------
830  * Register 0x2040: RXXG Configuration 1
831  *    Bit 15  RXXG_RXEN
832  *    Bit 14  RXXG_ROCF
833  *    Bit 13  RXXG_PAD_STRIP
834  *    Bit 10  RXXG_PUREP
835  *    Bit 9   RXXG_LONGP
836  *    Bit 8   RXXG_PARF
837  *    Bit 7   RXXG_FLCHK
838  *    Bit 5   RXXG_PASS_CTRL
839  *    Bit 3   RXXG_CRC_STRIP
840  *    Bit 2-0 RXXG_MIFG
841  *----------------------------------------------------------------------------*/
842 #define SUNI1x10GEXP_BITMSK_RXXG_RXEN       0x8000
843 #define SUNI1x10GEXP_BITMSK_RXXG_ROCF       0x4000
844 #define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP  0x2000
845 #define SUNI1x10GEXP_BITMSK_RXXG_PUREP      0x0400
846 #define SUNI1x10GEXP_BITMSK_RXXG_LONGP      0x0200
847 #define SUNI1x10GEXP_BITMSK_RXXG_PARF       0x0100
848 #define SUNI1x10GEXP_BITMSK_RXXG_FLCHK      0x0080
849 #define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL  0x0020
850 #define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP  0x0008
851 
852 /*----------------------------------------------------------------------------
853  * Register 0x02041: RXXG Configuration 2
854  *    Bit 7-0 RXXG_HDRSIZE
855  *----------------------------------------------------------------------------*/
856 #define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE  0x00FF
857 
858 /*----------------------------------------------------------------------------
859  * Register 0x2042: RXXG Configuration 3
860  *    Bit 15 RXXG_MIN_LERRE
861  *    Bit 14 RXXG_MAX_LERRE
862  *    Bit 12 RXXG_LINE_ERRE
863  *    Bit 10 RXXG_RX_OVRE
864  *    Bit 9  RXXG_ADR_FILTERE
865  *    Bit 8  RXXG_ERR_FILTERE
866  *    Bit 5  RXXG_PRMB_ERRE
867  *----------------------------------------------------------------------------*/
868 #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE     0x8000
869 #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE     0x4000
870 #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE     0x1000
871 #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE       0x0400
872 #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE   0x0200
873 #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE  0x0100
874 #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE     0x0020
875 
876 /*----------------------------------------------------------------------------
877  * Register 0x2043: RXXG Interrupt
878  *    Bit 15 RXXG_MIN_LERRI
879  *    Bit 14 RXXG_MAX_LERRI
880  *    Bit 12 RXXG_LINE_ERRI
881  *    Bit 10 RXXG_RX_OVRI
882  *    Bit 9  RXXG_ADR_FILTERI
883  *    Bit 8  RXXG_ERR_FILTERI
884  *    Bit 5  RXXG_PRMB_ERRE
885  *----------------------------------------------------------------------------*/
886 #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI    0x8000
887 #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI    0x4000
888 #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI    0x1000
889 #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI      0x0400
890 #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI  0x0200
891 #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI  0x0100
892 #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE    0x0020
893 
894 /*----------------------------------------------------------------------------
895  * Register 0x2049: RXXG Receive FIFO Threshold
896  *    Bit 2-0 RXXG_CUT_THRU
897  *----------------------------------------------------------------------------*/
898 #define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU  0x0007
899 #define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU  0
900 
901 /*----------------------------------------------------------------------------
902  * Register 0x2062H - 0x2069: RXXG Exact Match VID
903  *    Bit 11-0 RXXG_VID_MATCH
904  *----------------------------------------------------------------------------*/
905 #define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH  0x0FFF
906 #define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH  0
907 
908 /*----------------------------------------------------------------------------
909  * Register 0x206EH - 0x206F: RXXG Address Filter Control
910  *    Bit 3 RXXG_FORWARD_ENABLE
911  *    Bit 2 RXXG_VLAN_ENABLE
912  *    Bit 1 RXXG_SRC_ADDR
913  *    Bit 0 RXXG_MATCH_ENABLE
914  *----------------------------------------------------------------------------*/
915 #define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE  0x0008
916 #define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE     0x0004
917 #define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR        0x0002
918 #define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE    0x0001
919 
920 /*----------------------------------------------------------------------------
921  * Register 0x2070: RXXG Address Filter Control 2
922  *    Bit 1 RXXG_PMODE
923  *    Bit 0 RXXG_MHASH_EN
924  *----------------------------------------------------------------------------*/
925 #define SUNI1x10GEXP_BITMSK_RXXG_PMODE     0x0002
926 #define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN  0x0001
927 
928 /*----------------------------------------------------------------------------
929  * Register 0x2081: XRF Control Register 2
930  *    Bit 6   EN_PKT_GEN
931  *    Bit 4-2 PATT
932  *----------------------------------------------------------------------------*/
933 #define SUNI1x10GEXP_BITMSK_EN_PKT_GEN  0x0040
934 #define SUNI1x10GEXP_BITMSK_PATT        0x001C
935 #define SUNI1x10GEXP_BITOFF_PATT        2
936 
937 /*----------------------------------------------------------------------------
938  * Register 0x2088: XRF Interrupt Enable
939  *    Bit 12-9 LANE_HICERE
940  *    Bit 8-5  HS_SD_LANEE
941  *    Bit 4    ALIGN_STATUS_ERRE
942  *    Bit 3-0  LANE_SYNC_STAT_ERRE
943  *----------------------------------------------------------------------------*/
944 #define SUNI1x10GEXP_BITMSK_LANE_HICERE          0x1E00
945 #define SUNI1x10GEXP_BITOFF_LANE_HICERE          9
946 #define SUNI1x10GEXP_BITMSK_HS_SD_LANEE          0x01E0
947 #define SUNI1x10GEXP_BITOFF_HS_SD_LANEE          5
948 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE    0x0010
949 #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE  0x000F
950 #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE  0
951 
952 /*----------------------------------------------------------------------------
953  * Register 0x2089: XRF Interrupt Status
954  *    Bit 12-9 LANE_HICERI
955  *    Bit 8-5  HS_SD_LANEI
956  *    Bit 4    ALIGN_STATUS_ERRI
957  *    Bit 3-0  LANE_SYNC_STAT_ERRI
958  *----------------------------------------------------------------------------*/
959 #define SUNI1x10GEXP_BITMSK_LANE_HICERI          0x1E00
960 #define SUNI1x10GEXP_BITOFF_LANE_HICERI          9
961 #define SUNI1x10GEXP_BITMSK_HS_SD_LANEI          0x01E0
962 #define SUNI1x10GEXP_BITOFF_HS_SD_LANEI          5
963 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI    0x0010
964 #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI  0x000F
965 #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI  0
966 
967 /*----------------------------------------------------------------------------
968  * Register 0x208A: XRF Error Status
969  *    Bit 8-5  HS_SD_LANE
970  *    Bit 4    ALIGN_STATUS_ERR
971  *    Bit 3-0  LANE_SYNC_STAT_ERR
972  *----------------------------------------------------------------------------*/
973 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE3          0x0100
974 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE2          0x0080
975 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE1          0x0040
976 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE0          0x0020
977 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR     0x0010
978 #define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR  0x0008
979 #define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR  0x0004
980 #define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR  0x0002
981 #define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR  0x0001
982 
983 /*----------------------------------------------------------------------------
984  * Register 0x208B: XRF Diagnostic Interrupt Enable
985  *    Bit 7-4 LANE_OVERRUNE
986  *    Bit 3-0 LANE_UNDERRUNE
987  *----------------------------------------------------------------------------*/
988 #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE   0x00F0
989 #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE   4
990 #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE  0x000F
991 #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE  0
992 
993 /*----------------------------------------------------------------------------
994  * Register 0x208C: XRF Diagnostic Interrupt Status
995  *    Bit 7-4 LANE_OVERRUNI
996  *    Bit 3-0 LANE_UNDERRUNI
997  *----------------------------------------------------------------------------*/
998 #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI   0x00F0
999 #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI   4
1000 #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI  0x000F
1001 #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI  0
1002 
1003 /*----------------------------------------------------------------------------
1004  * Register 0x20C0: RXOAM Configuration
1005  *    Bit 15    RXOAM_BUSY
1006  *    Bit 14-12 RXOAM_F2_SEL
1007  *    Bit 10-8  RXOAM_F1_SEL
1008  *    Bit 7-6   RXOAM_FILTER_CTRL
1009  *    Bit 5-0   RXOAM_PX_EN
1010  *----------------------------------------------------------------------------*/
1011 #define SUNI1x10GEXP_BITMSK_RXOAM_BUSY         0x8000
1012 #define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL       0x7000
1013 #define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL       12
1014 #define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL       0x0700
1015 #define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL       8
1016 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL  0x00C0
1017 #define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL  6
1018 #define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN        0x003F
1019 #define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN        0
1020 
1021 /*----------------------------------------------------------------------------
1022  * Register 0x20C1,0x20C2: RXOAM Filter Configuration
1023  *    Bit 15-8 RXOAM_FX_MASK
1024  *    Bit 7-0  RXOAM_FX_VAL
1025  *----------------------------------------------------------------------------*/
1026 #define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK  0xFF00
1027 #define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK  8
1028 #define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL   0x00FF
1029 #define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl   0
1030 
1031 /*----------------------------------------------------------------------------
1032  * Register 0x20C3: RXOAM Configuration Register 2
1033  *    Bit 13    RXOAM_REC_BYTE_VAL
1034  *    Bit 11-10 RXOAM_BYPASS_MODE
1035  *    Bit 5-0   RXOAM_PX_CLEAR
1036  *----------------------------------------------------------------------------*/
1037 #define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL  0x2000
1038 #define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE   0x0C00
1039 #define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE   10
1040 #define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR      0x003F
1041 #define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR      0
1042 
1043 /*----------------------------------------------------------------------------
1044  * Register 0x20C4: RXOAM HEC Configuration
1045  *    Bit 15-8 RXOAM_COSET
1046  *    Bit 2    RXOAM_HEC_ERR_PKT
1047  *    Bit 0    RXOAM_HEC_EN
1048  *----------------------------------------------------------------------------*/
1049 #define SUNI1x10GEXP_BITMSK_RXOAM_COSET        0xFF00
1050 #define SUNI1x10GEXP_BITOFF_RXOAM_COSET        8
1051 #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT  0x0004
1052 #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN       0x0001
1053 
1054 /*----------------------------------------------------------------------------
1055  * Register 0x20C7: RXOAM Interrupt Enable
1056  *    Bit 10 RXOAM_FILTER_THRSHE
1057  *    Bit 9  RXOAM_OAM_ERRE
1058  *    Bit 8  RXOAM_HECE_THRSHE
1059  *    Bit 7  RXOAM_SOPE
1060  *    Bit 6  RXOAM_RFE
1061  *    Bit 5  RXOAM_LFE
1062  *    Bit 4  RXOAM_DV_ERRE
1063  *    Bit 3  RXOAM_DATA_INVALIDE
1064  *    Bit 2  RXOAM_FILTER_DROPE
1065  *    Bit 1  RXOAM_HECE
1066  *    Bit 0  RXOAM_OFLE
1067  *----------------------------------------------------------------------------*/
1068 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE  0x0400
1069 #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE       0x0200
1070 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE    0x0100
1071 #define SUNI1x10GEXP_BITMSK_RXOAM_SOPE           0x0080
1072 #define SUNI1x10GEXP_BITMSK_RXOAM_RFE            0x0040
1073 #define SUNI1x10GEXP_BITMSK_RXOAM_LFE            0x0020
1074 #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE        0x0010
1075 #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE  0x0008
1076 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE   0x0004
1077 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE           0x0002
1078 #define SUNI1x10GEXP_BITMSK_RXOAM_OFLE           0x0001
1079 
1080 /*----------------------------------------------------------------------------
1081  * Register 0x20C8: RXOAM Interrupt Status
1082  *    Bit 10 RXOAM_FILTER_THRSHI
1083  *    Bit 9  RXOAM_OAM_ERRI
1084  *    Bit 8  RXOAM_HECE_THRSHI
1085  *    Bit 7  RXOAM_SOPI
1086  *    Bit 6  RXOAM_RFI
1087  *    Bit 5  RXOAM_LFI
1088  *    Bit 4  RXOAM_DV_ERRI
1089  *    Bit 3  RXOAM_DATA_INVALIDI
1090  *    Bit 2  RXOAM_FILTER_DROPI
1091  *    Bit 1  RXOAM_HECI
1092  *    Bit 0  RXOAM_OFLI
1093  *----------------------------------------------------------------------------*/
1094 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI  0x0400
1095 #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI       0x0200
1096 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI    0x0100
1097 #define SUNI1x10GEXP_BITMSK_RXOAM_SOPI           0x0080
1098 #define SUNI1x10GEXP_BITMSK_RXOAM_RFI            0x0040
1099 #define SUNI1x10GEXP_BITMSK_RXOAM_LFI            0x0020
1100 #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI        0x0010
1101 #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI  0x0008
1102 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI   0x0004
1103 #define SUNI1x10GEXP_BITMSK_RXOAM_HECI           0x0002
1104 #define SUNI1x10GEXP_BITMSK_RXOAM_OFLI           0x0001
1105 
1106 /*----------------------------------------------------------------------------
1107  * Register 0x20C9: RXOAM Status
1108  *    Bit 10 RXOAM_FILTER_THRSHV
1109  *    Bit 8  RXOAM_HECE_THRSHV
1110  *    Bit 6  RXOAM_RFV
1111  *    Bit 5  RXOAM_LFV
1112  *----------------------------------------------------------------------------*/
1113 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV  0x0400
1114 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV    0x0100
1115 #define SUNI1x10GEXP_BITMSK_RXOAM_RFV            0x0040
1116 #define SUNI1x10GEXP_BITMSK_RXOAM_LFV            0x0020
1117 
1118 /*----------------------------------------------------------------------------
1119  * Register 0x2100: MSTAT Control
1120  *    Bit 2 MSTAT_WRITE
1121  *    Bit 1 MSTAT_CLEAR
1122  *    Bit 0 MSTAT_SNAP
1123  *----------------------------------------------------------------------------*/
1124 #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE  0x0004
1125 #define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR  0x0002
1126 #define SUNI1x10GEXP_BITMSK_MSTAT_SNAP   0x0001
1127 
1128 /*----------------------------------------------------------------------------
1129  * Register 0x2109: MSTAT Counter Write Address
1130  *    Bit 5-0 MSTAT_WRITE_ADDRESS
1131  *----------------------------------------------------------------------------*/
1132 #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F
1133 #define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0
1134 
1135 /*----------------------------------------------------------------------------
1136  * Register 0x2200: IFLX Global Configuration Register
1137  *    Bit 15   IFLX_IRCU_ENABLE
1138  *    Bit 14   IFLX_IDSWT_ENABLE
1139  *    Bit 13-0 IFLX_IFD_CNT
1140  *----------------------------------------------------------------------------*/
1141 #define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE   0x8000
1142 #define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE  0x4000
1143 #define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT       0x3FFF
1144 #define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT       0
1145 
1146 /*----------------------------------------------------------------------------
1147  * Register 0x2209: IFLX FIFO Overflow Enable
1148  *    Bit 0 IFLX_OVFE
1149  *----------------------------------------------------------------------------*/
1150 #define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x0001
1151 
1152 /*----------------------------------------------------------------------------
1153  * Register 0x220A: IFLX FIFO Overflow Interrupt
1154  *    Bit 0 IFLX_OVFI
1155  *----------------------------------------------------------------------------*/
1156 #define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x0001
1157 
1158 /*----------------------------------------------------------------------------
1159  * Register 0x220D: IFLX Indirect Channel Address
1160  *    Bit 15 IFLX_BUSY
1161  *    Bit 14 IFLX_RWB
1162  *----------------------------------------------------------------------------*/
1163 #define SUNI1x10GEXP_BITMSK_IFLX_BUSY  0x8000
1164 #define SUNI1x10GEXP_BITMSK_IFLX_RWB   0x4000
1165 
1166 /*----------------------------------------------------------------------------
1167  * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision
1168  *    Bit 9-0 IFLX_LOLIM
1169  *----------------------------------------------------------------------------*/
1170 #define SUNI1x10GEXP_BITMSK_IFLX_LOLIM  0x03FF
1171 #define SUNI1x10GEXP_BITOFF_IFLX_LOLIM  0
1172 
1173 /*----------------------------------------------------------------------------
1174  * Register 0x220F: IFLX Indirect Logical FIFO High Limit
1175  *    Bit 9-0 IFLX_HILIM
1176  *----------------------------------------------------------------------------*/
1177 #define SUNI1x10GEXP_BITMSK_IFLX_HILIM  0x03FF
1178 #define SUNI1x10GEXP_BITOFF_IFLX_HILIM  0
1179 
1180 /*----------------------------------------------------------------------------
1181  * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit
1182  *    Bit 15   IFLX_FULL
1183  *    Bit 14   IFLX_AFULL
1184  *    Bit 13-0 IFLX_AFTH
1185  *----------------------------------------------------------------------------*/
1186 #define SUNI1x10GEXP_BITMSK_IFLX_FULL   0x8000
1187 #define SUNI1x10GEXP_BITMSK_IFLX_AFULL  0x4000
1188 #define SUNI1x10GEXP_BITMSK_IFLX_AFTH   0x3FFF
1189 #define SUNI1x10GEXP_BITOFF_IFLX_AFTH   0
1190 
1191 /*----------------------------------------------------------------------------
1192  * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit
1193  *    Bit 15   IFLX_EMPTY
1194  *    Bit 14   IFLX_AEMPTY
1195  *    Bit 13-0 IFLX_AETH
1196  *----------------------------------------------------------------------------*/
1197 #define SUNI1x10GEXP_BITMSK_IFLX_EMPTY   0x8000
1198 #define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY  0x4000
1199 #define SUNI1x10GEXP_BITMSK_IFLX_AETH    0x3FFF
1200 #define SUNI1x10GEXP_BITOFF_IFLX_AETH    0
1201 
1202 /*----------------------------------------------------------------------------
1203  * Register 0x2240: PL4MOS Configuration Register
1204  *    Bit 3 PL4MOS_RE_INIT
1205  *    Bit 2 PL4MOS_EN
1206  *    Bit 1 PL4MOS_NO_STATUS
1207  *----------------------------------------------------------------------------*/
1208 #define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT          0x0008
1209 #define SUNI1x10GEXP_BITMSK_PL4MOS_EN               0x0004
1210 #define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS        0x0002
1211 
1212 /*----------------------------------------------------------------------------
1213  * Register 0x2243: PL4MOS MaxBurst1 Register
1214  *    Bit 11-0 PL4MOS_MAX_BURST1
1215  *----------------------------------------------------------------------------*/
1216 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1  0x0FFF
1217 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1  0
1218 
1219 /*----------------------------------------------------------------------------
1220  * Register 0x2244: PL4MOS MaxBurst2 Register
1221  *    Bit 11-0 PL4MOS_MAX_BURST2
1222  *----------------------------------------------------------------------------*/
1223 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2  0x0FFF
1224 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2  0
1225 
1226 /*----------------------------------------------------------------------------
1227  * Register 0x2245: PL4MOS Transfer Size Register
1228  *    Bit 7-0 PL4MOS_MAX_TRANSFER
1229  *----------------------------------------------------------------------------*/
1230 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER  0x00FF
1231 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER  0
1232 
1233 /*----------------------------------------------------------------------------
1234  * Register 0x2280: PL4ODP Configuration
1235  *    Bit 15-12 PL4ODP_REPEAT_T
1236  *    Bit 8     PL4ODP_SOP_RULE
1237  *    Bit 1     PL4ODP_EN_PORTS
1238  *    Bit 0     PL4ODP_EN_DFWD
1239  *----------------------------------------------------------------------------*/
1240 #define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T   0xF000
1241 #define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T   12
1242 #define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE   0x0100
1243 #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS   0x0002
1244 #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD    0x0001
1245 
1246 /*----------------------------------------------------------------------------
1247  * Register 0x2282: PL4ODP Interrupt Mask
1248  *    Bit 0 PL4ODP_OUT_DISE
1249  *----------------------------------------------------------------------------*/
1250 #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE     0x0001
1251 
1252 
1253 
1254 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE  0x0080
1255 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE  0x0040
1256 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE    0x0008
1257 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE    0x0004
1258 #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE      0x0002
1259 
1260 
1261 /*----------------------------------------------------------------------------
1262  * Register 0x2283: PL4ODP Interrupt
1263  *    Bit 0 PL4ODP_OUT_DISI
1264  *----------------------------------------------------------------------------*/
1265 #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI     0x0001
1266 
1267 
1268 
1269 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI  0x0080
1270 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI  0x0040
1271 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI    0x0008
1272 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI    0x0004
1273 #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI      0x0002
1274 
1275 /*----------------------------------------------------------------------------
1276  * Register 0x2300:  PL4IO Lock Detect Status
1277  *    Bit 15 PL4IO_OUT_ROOLV
1278  *    Bit 12 PL4IO_IS_ROOLV
1279  *    Bit 11 PL4IO_DIP2_ERRV
1280  *    Bit 8  PL4IO_ID_ROOLV
1281  *    Bit 4  PL4IO_IS_DOOLV
1282  *    Bit 0  PL4IO_ID_DOOLV
1283  *----------------------------------------------------------------------------*/
1284 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV  0x8000
1285 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV   0x1000
1286 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV  0x0800
1287 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV   0x0100
1288 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV   0x0010
1289 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV   0x0001
1290 
1291 /*----------------------------------------------------------------------------
1292  * Register 0x2301:  PL4IO Lock Detect Change
1293  *    Bit 15 PL4IO_OUT_ROOLI
1294  *    Bit 12 PL4IO_IS_ROOLI
1295  *    Bit 11 PL4IO_DIP2_ERRI
1296  *    Bit 8  PL4IO_ID_ROOLI
1297  *    Bit 4  PL4IO_IS_DOOLI
1298  *    Bit 0  PL4IO_ID_DOOLI
1299  *----------------------------------------------------------------------------*/
1300 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI  0x8000
1301 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI   0x1000
1302 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI  0x0800
1303 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI   0x0100
1304 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI   0x0010
1305 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI   0x0001
1306 
1307 /*----------------------------------------------------------------------------
1308  * Register 0x2302:  PL4IO Lock Detect Mask
1309  *    Bit 15 PL4IO_OUT_ROOLE
1310  *    Bit 12 PL4IO_IS_ROOLE
1311  *    Bit 11 PL4IO_DIP2_ERRE
1312  *    Bit 8  PL4IO_ID_ROOLE
1313  *    Bit 4  PL4IO_IS_DOOLE
1314  *    Bit 0  PL4IO_ID_DOOLE
1315  *----------------------------------------------------------------------------*/
1316 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE  0x8000
1317 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE   0x1000
1318 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE  0x0800
1319 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE   0x0100
1320 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE   0x0010
1321 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE   0x0001
1322 
1323 /*----------------------------------------------------------------------------
1324  * Register 0x2303:  PL4IO Lock Detect Limits
1325  *    Bit 15-8 PL4IO_REF_LIMIT
1326  *    Bit 7-0  PL4IO_TRAN_LIMIT
1327  *----------------------------------------------------------------------------*/
1328 #define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT   0xFF00
1329 #define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT   8
1330 #define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT  0x00FF
1331 #define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT  0
1332 
1333 /*----------------------------------------------------------------------------
1334  * Register 0x2304:  PL4IO Calendar Repetitions
1335  *    Bit 15-8 PL4IO_IN_MUL
1336  *    Bit 7-0  PL4IO_OUT_MUL
1337  *----------------------------------------------------------------------------*/
1338 #define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL   0xFF00
1339 #define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL   8
1340 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL  0x00FF
1341 #define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL  0
1342 
1343 /*----------------------------------------------------------------------------
1344  * Register 0x2305:  PL4IO Configuration
1345  *    Bit 15  PL4IO_DIP2_ERR_CHK
1346  *    Bit 11  PL4IO_ODAT_DIS
1347  *    Bit 10  PL4IO_TRAIN_DIS
1348  *    Bit 9   PL4IO_OSTAT_DIS
1349  *    Bit 8   PL4IO_ISTAT_DIS
1350  *    Bit 7   PL4IO_NO_ISTAT
1351  *    Bit 6   PL4IO_STAT_OUTSEL
1352  *    Bit 5   PL4IO_INSEL
1353  *    Bit 4   PL4IO_DLSEL
1354  *    Bit 1-0 PL4IO_OUTSEL
1355  *----------------------------------------------------------------------------*/
1356 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK  0x8000
1357 #define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS      0x0800
1358 #define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS     0x0400
1359 #define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS     0x0200
1360 #define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS     0x0100
1361 #define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT      0x0080
1362 #define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL   0x0040
1363 #define SUNI1x10GEXP_BITMSK_PL4IO_INSEL         0x0020
1364 #define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL         0x0010
1365 #define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL        0x0003
1366 #define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL        0
1367 
1368 /*----------------------------------------------------------------------------
1369  * Register 0x3040: TXXG Configuration Register 1
1370  *    Bit 15   TXXG_TXEN0
1371  *    Bit 13   TXXG_HOSTPAUSE
1372  *    Bit 12-7 TXXG_IPGT
1373  *    Bit 5    TXXG_32BIT_ALIGN
1374  *    Bit 4    TXXG_CRCEN
1375  *    Bit 3    TXXG_FCTX
1376  *    Bit 2    TXXG_FCRX
1377  *    Bit 1    TXXG_PADEN
1378  *    Bit 0    TXXG_SPRE
1379  *----------------------------------------------------------------------------*/
1380 #define SUNI1x10GEXP_BITMSK_TXXG_TXEN0        0x8000
1381 #define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE    0x2000
1382 #define SUNI1x10GEXP_BITMSK_TXXG_IPGT         0x1F80
1383 #define SUNI1x10GEXP_BITOFF_TXXG_IPGT         7
1384 #define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN  0x0020
1385 #define SUNI1x10GEXP_BITMSK_TXXG_CRCEN        0x0010
1386 #define SUNI1x10GEXP_BITMSK_TXXG_FCTX         0x0008
1387 #define SUNI1x10GEXP_BITMSK_TXXG_FCRX         0x0004
1388 #define SUNI1x10GEXP_BITMSK_TXXG_PADEN        0x0002
1389 #define SUNI1x10GEXP_BITMSK_TXXG_SPRE         0x0001
1390 
1391 /*----------------------------------------------------------------------------
1392  * Register 0x3041: TXXG Configuration Register 2
1393  *    Bit 7-0   TXXG_HDRSIZE
1394  *----------------------------------------------------------------------------*/
1395 #define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE  0x00FF
1396 
1397 /*----------------------------------------------------------------------------
1398  * Register 0x3042: TXXG Configuration Register 3
1399  *    Bit 15 TXXG_FIFO_ERRE
1400  *    Bit 14 TXXG_FIFO_UDRE
1401  *    Bit 13 TXXG_MAX_LERRE
1402  *    Bit 12 TXXG_MIN_LERRE
1403  *    Bit 11 TXXG_XFERE
1404  *----------------------------------------------------------------------------*/
1405 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE  0x8000
1406 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE  0x4000
1407 #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE  0x2000
1408 #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE  0x1000
1409 #define SUNI1x10GEXP_BITMSK_TXXG_XFERE      0x0800
1410 
1411 /*----------------------------------------------------------------------------
1412  * Register 0x3043: TXXG Interrupt
1413  *    Bit 15 TXXG_FIFO_ERRI
1414  *    Bit 14 TXXG_FIFO_UDRI
1415  *    Bit 13 TXXG_MAX_LERRI
1416  *    Bit 12 TXXG_MIN_LERRI
1417  *    Bit 11 TXXG_XFERI
1418  *----------------------------------------------------------------------------*/
1419 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI  0x8000
1420 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI  0x4000
1421 #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI  0x2000
1422 #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI  0x1000
1423 #define SUNI1x10GEXP_BITMSK_TXXG_XFERI      0x0800
1424 
1425 /*----------------------------------------------------------------------------
1426  * Register 0x3044: TXXG Status Register
1427  *    Bit 1 TXXG_TXACTIVE
1428  *    Bit 0 TXXG_PAUSED
1429  *----------------------------------------------------------------------------*/
1430 #define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE  0x0002
1431 #define SUNI1x10GEXP_BITMSK_TXXG_PAUSED    0x0001
1432 
1433 /*----------------------------------------------------------------------------
1434  * Register 0x3046: TXXG TX_MINFR -  Transmit Min Frame Size Register
1435  *    Bit 7-0 TXXG_TX_MINFR
1436  *----------------------------------------------------------------------------*/
1437 #define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR  0x00FF
1438 #define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR  0
1439 
1440 /*----------------------------------------------------------------------------
1441  * Register 0x3052: TXXG Pause Quantum Value Configuration Register
1442  *    Bit 7-0 TXXG_FC_PAUSE_QNTM
1443  *----------------------------------------------------------------------------*/
1444 #define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM  0x00FF
1445 #define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM  0
1446 
1447 /*----------------------------------------------------------------------------
1448  * Register 0x3080: XTEF Control
1449  *    Bit 3-0 XTEF_FORCE_PARITY_ERR
1450  *----------------------------------------------------------------------------*/
1451 #define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR  0x000F
1452 #define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR  0
1453 
1454 /*----------------------------------------------------------------------------
1455  * Register 0x3084: XTEF Interrupt Event Register
1456  *    Bit 0 XTEF_LOST_SYNCI
1457  *----------------------------------------------------------------------------*/
1458 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI  0x0001
1459 
1460 /*----------------------------------------------------------------------------
1461  * Register 0x3085: XTEF Interrupt Enable Register
1462  *    Bit 0 XTEF_LOST_SYNCE
1463  *----------------------------------------------------------------------------*/
1464 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE  0x0001
1465 
1466 /*----------------------------------------------------------------------------
1467  * Register 0x3086: XTEF Visibility Register
1468  *    Bit 0 XTEF_LOST_SYNCV
1469  *----------------------------------------------------------------------------*/
1470 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV  0x0001
1471 
1472 /*----------------------------------------------------------------------------
1473  * Register 0x30C0: TXOAM OAM Configuration
1474  *    Bit 15   TXOAM_HEC_EN
1475  *    Bit 14   TXOAM_EMPTYCODE_EN
1476  *    Bit 13   TXOAM_FORCE_IDLE
1477  *    Bit 12   TXOAM_IGNORE_IDLE
1478  *    Bit 11-6 TXOAM_PX_OVERWRITE
1479  *    Bit 5-0  TXOAM_PX_SEL
1480  *----------------------------------------------------------------------------*/
1481 #define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN        0x8000
1482 #define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN  0x4000
1483 #define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE    0x2000
1484 #define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE   0x1000
1485 #define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE  0x0FC0
1486 #define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE  6
1487 #define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL        0x003F
1488 #define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL        0
1489 
1490 /*----------------------------------------------------------------------------
1491  * Register 0x30C1: TXOAM Mini-Packet Rate Configuration
1492  *    Bit 15   TXOAM_MINIDIS
1493  *    Bit 14   TXOAM_BUSY
1494  *    Bit 13   TXOAM_TRANS_EN
1495  *    Bit 10-0 TXOAM_MINIRATE
1496  *----------------------------------------------------------------------------*/
1497 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS   0x8000
1498 #define SUNI1x10GEXP_BITMSK_TXOAM_BUSY      0x4000
1499 #define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN  0x2000
1500 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE  0x07FF
1501 
1502 /*----------------------------------------------------------------------------
1503  * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration
1504  *    Bit 13-10 TXOAM_FTHRESH
1505  *    Bit 9-6   TXOAM_MINIPOST
1506  *    Bit 5-0   TXOAM_MINIPRE
1507  *----------------------------------------------------------------------------*/
1508 #define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH   0x3C00
1509 #define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH   10
1510 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST  0x03C0
1511 #define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST  6
1512 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE   0x003F
1513 
1514 /*----------------------------------------------------------------------------
1515  * Register 0x30C6: TXOAM Interrupt Enable
1516  *    Bit 2 TXOAM_SOP_ERRE
1517  *    Bit 1 TXOAM_OFLE
1518  *    Bit 0 TXOAM_ERRE
1519  *----------------------------------------------------------------------------*/
1520 #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE    0x0004
1521 #define SUNI1x10GEXP_BITMSK_TXOAM_OFLE        0x0002
1522 #define SUNI1x10GEXP_BITMSK_TXOAM_ERRE        0x0001
1523 
1524 /*----------------------------------------------------------------------------
1525  * Register 0x30C7: TXOAM Interrupt Status
1526  *    Bit 2 TXOAM_SOP_ERRI
1527  *    Bit 1 TXOAM_OFLI
1528  *    Bit 0 TXOAM_ERRI
1529  *----------------------------------------------------------------------------*/
1530 #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI    0x0004
1531 #define SUNI1x10GEXP_BITMSK_TXOAM_OFLI        0x0002
1532 #define SUNI1x10GEXP_BITMSK_TXOAM_ERRI        0x0001
1533 
1534 /*----------------------------------------------------------------------------
1535  * Register 0x30CF: TXOAM Coset
1536  *    Bit 7-0 TXOAM_COSET
1537  *----------------------------------------------------------------------------*/
1538 #define SUNI1x10GEXP_BITMSK_TXOAM_COSET  0x00FF
1539 
1540 /*----------------------------------------------------------------------------
1541  * Register 0x3200: EFLX Global Configuration
1542  *    Bit 15 EFLX_ERCU_EN
1543  *    Bit 7  EFLX_EN_EDSWT
1544  *----------------------------------------------------------------------------*/
1545 #define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN   0x8000
1546 #define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT  0x0080
1547 
1548 /*----------------------------------------------------------------------------
1549  * Register 0x3201: EFLX ERCU Global Status
1550  *    Bit 13 EFLX_OVF_ERR
1551  *----------------------------------------------------------------------------*/
1552 #define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR  0x2000
1553 
1554 /*----------------------------------------------------------------------------
1555  * Register 0x3202: EFLX Indirect Channel Address
1556  *    Bit 15 EFLX_BUSY
1557  *    Bit 14 EFLX_RDWRB
1558  *----------------------------------------------------------------------------*/
1559 #define SUNI1x10GEXP_BITMSK_EFLX_BUSY   0x8000
1560 #define SUNI1x10GEXP_BITMSK_EFLX_RDWRB  0x4000
1561 
1562 /*----------------------------------------------------------------------------
1563  * Register 0x3203: EFLX Indirect Logical FIFO Low Limit
1564  *----------------------------------------------------------------------------*/
1565 #define SUNI1x10GEXP_BITMSK_EFLX_LOLIM                    0x03FF
1566 #define SUNI1x10GEXP_BITOFF_EFLX_LOLIM                    0
1567 
1568 /*----------------------------------------------------------------------------
1569  * Register 0x3204: EFLX Indirect Logical FIFO High Limit
1570  *----------------------------------------------------------------------------*/
1571 #define SUNI1x10GEXP_BITMSK_EFLX_HILIM                    0x03FF
1572 #define SUNI1x10GEXP_BITOFF_EFLX_HILIM                    0
1573 
1574 /*----------------------------------------------------------------------------
1575  * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit
1576  *    Bit 15   EFLX_FULL
1577  *    Bit 14   EFLX_AFULL
1578  *    Bit 13-0 EFLX_AFTH
1579  *----------------------------------------------------------------------------*/
1580 #define SUNI1x10GEXP_BITMSK_EFLX_FULL   0x8000
1581 #define SUNI1x10GEXP_BITMSK_EFLX_AFULL  0x4000
1582 #define SUNI1x10GEXP_BITMSK_EFLX_AFTH   0x3FFF
1583 #define SUNI1x10GEXP_BITOFF_EFLX_AFTH   0
1584 
1585 /*----------------------------------------------------------------------------
1586  * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit
1587  *    Bit 15   EFLX_EMPTY
1588  *    Bit 14   EFLX_AEMPTY
1589  *    Bit 13-0 EFLX_AETH
1590  *----------------------------------------------------------------------------*/
1591 #define SUNI1x10GEXP_BITMSK_EFLX_EMPTY   0x8000
1592 #define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY  0x4000
1593 #define SUNI1x10GEXP_BITMSK_EFLX_AETH    0x3FFF
1594 #define SUNI1x10GEXP_BITOFF_EFLX_AETH    0
1595 
1596 /*----------------------------------------------------------------------------
1597  * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold
1598  *----------------------------------------------------------------------------*/
1599 #define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU                 0x3FFF
1600 #define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU                 0
1601 
1602 /*----------------------------------------------------------------------------
1603  * Register 0x320C: EFLX FIFO Overflow Error Enable
1604  *    Bit 0 EFLX_OVFE
1605  *----------------------------------------------------------------------------*/
1606 #define SUNI1x10GEXP_BITMSK_EFLX_OVFE  0x0001
1607 
1608 /*----------------------------------------------------------------------------
1609  * Register 0x320D: EFLX FIFO Overflow Error Indication
1610  *    Bit 0 EFLX_OVFI
1611  *----------------------------------------------------------------------------*/
1612 #define SUNI1x10GEXP_BITMSK_EFLX_OVFI  0x0001
1613 
1614 /*----------------------------------------------------------------------------
1615  * Register 0x3210: EFLX Channel Provision
1616  *    Bit 0 EFLX_PROV
1617  *----------------------------------------------------------------------------*/
1618 #define SUNI1x10GEXP_BITMSK_EFLX_PROV  0x0001
1619 
1620 /*----------------------------------------------------------------------------
1621  * Register 0x3280: PL4IDU Configuration
1622  *    Bit 2 PL4IDU_SYNCH_ON_TRAIN
1623  *    Bit 1 PL4IDU_EN_PORTS
1624  *    Bit 0 PL4IDU_EN_DFWD
1625  *----------------------------------------------------------------------------*/
1626 #define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN  0x0004
1627 #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS        0x0002
1628 #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD         0x0001
1629 
1630 /*----------------------------------------------------------------------------
1631  * Register 0x3282: PL4IDU Interrupt Mask
1632  *    Bit 1 PL4IDU_DIP4E
1633  *----------------------------------------------------------------------------*/
1634 #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E       0x0002
1635 
1636 /*----------------------------------------------------------------------------
1637  * Register 0x3283: PL4IDU Interrupt
1638  *    Bit 1 PL4IDU_DIP4I
1639  *----------------------------------------------------------------------------*/
1640 #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I       0x0002
1641 
1642 #endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */
1643 
1644