1 /*
2 * derived from linux/arch/arm/mach-versatile/core.c
3 * linux/arch/arm/mach-bcmring/core.c
4 *
5 * Copyright (C) 1999 - 2003 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22 /* Portions copyright Broadcom 2008 */
23
24 #include <linux/init.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/sysdev.h>
29 #include <linux/interrupt.h>
30 #include <linux/amba/bus.h>
31 #include <linux/clocksource.h>
32 #include <linux/clockchips.h>
33 #include <linux/clkdev.h>
34
35 #include <mach/csp/mm_addr.h>
36 #include <mach/hardware.h>
37 #include <linux/io.h>
38 #include <asm/irq.h>
39 #include <asm/hardware/arm_timer.h>
40 #include <asm/mach-types.h>
41
42 #include <asm/mach/arch.h>
43 #include <asm/mach/flash.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
46 #include <asm/mach/map.h>
47
48 #include <cfg_global.h>
49
50 #include "clock.h"
51
52 #include <csp/secHw.h>
53 #include <mach/csp/secHw_def.h>
54 #include <mach/csp/chipcHw_inline.h>
55 #include <mach/csp/tmrHw_reg.h>
56
57 #define AMBA_DEVICE(name, initname, base, plat, size) \
58 static struct amba_device name##_device = { \
59 .dev = { \
60 .coherent_dma_mask = ~0, \
61 .init_name = initname, \
62 .platform_data = plat \
63 }, \
64 .res = { \
65 .start = MM_ADDR_IO_##base, \
66 .end = MM_ADDR_IO_##base + (size) - 1, \
67 .flags = IORESOURCE_MEM \
68 }, \
69 .dma_mask = ~0, \
70 .irq = { \
71 IRQ_##base \
72 } \
73 }
74
75
76 AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
77 AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
78
79 static struct clk pll1_clk = {
80 .name = "PLL1",
81 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
82 .rate_hz = 2000000000,
83 .use_cnt = 7,
84 };
85
86 static struct clk uart_clk = {
87 .name = "UART",
88 .type = CLK_TYPE_PROGRAMMABLE,
89 .csp_id = chipcHw_CLOCK_UART,
90 .rate_hz = HW_CFG_UART_CLK_HZ,
91 .parent = &pll1_clk,
92 };
93
94 static struct clk dummy_apb_pclk = {
95 .name = "BUSCLK",
96 .type = CLK_TYPE_PRIMARY,
97 .mode = CLK_MODE_XTAL,
98 };
99
100 static struct clk_lookup lookups[] = {
101 { /* Bus clock */
102 .con_id = "apb_pclk",
103 .clk = &dummy_apb_pclk,
104 }, { /* UART0 */
105 .dev_id = "uarta",
106 .clk = &uart_clk,
107 }, { /* UART1 */
108 .dev_id = "uartb",
109 .clk = &uart_clk,
110 }
111 };
112
113 static struct amba_device *amba_devs[] __initdata = {
114 &uartA_device,
115 &uartB_device,
116 };
117
bcmring_amba_init(void)118 void __init bcmring_amba_init(void)
119 {
120 int i;
121 u32 bus_clock;
122
123 /* Linux is run initially in non-secure mode. Secure peripherals */
124 /* generate FIQ, and must be handled in secure mode. Until we have */
125 /* a linux security monitor implementation, keep everything in */
126 /* non-secure mode. */
127 chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
128 secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
129 secHw_BLK_MASK_KEY_SCAN |
130 secHw_BLK_MASK_TOUCH_SCREEN |
131 secHw_BLK_MASK_UART0 |
132 secHw_BLK_MASK_UART1 |
133 secHw_BLK_MASK_WATCHDOG |
134 secHw_BLK_MASK_SPUM |
135 secHw_BLK_MASK_DDR2 |
136 secHw_BLK_MASK_SPU |
137 secHw_BLK_MASK_PKA |
138 secHw_BLK_MASK_RNG |
139 secHw_BLK_MASK_RTC |
140 secHw_BLK_MASK_OTP |
141 secHw_BLK_MASK_BOOT |
142 secHw_BLK_MASK_MPU |
143 secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
144
145 /* Only the devices attached to the AMBA bus are enabled just before the bus is */
146 /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
147 /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
148 /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
149 bus_clock = chipcHw_REG_BUS_CLOCK_GE
150 | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
151
152 chipcHw_busInterfaceClockEnable(bus_clock);
153
154 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
155
156 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
157 struct amba_device *d = amba_devs[i];
158 amba_device_register(d, &iomem_resource);
159 }
160 }
161
162 /*
163 * Where is the timer (VA)?
164 */
165 #define TIMER0_VA_BASE MM_IO_BASE_TMR
166 #define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20)
167 #define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40)
168 #define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60)
169
170 /* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
171 #if defined(CONFIG_ARCH_FPGA11107)
172 /* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
173 /* slow down Linux's sense of time */
174 #define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
175 #define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
176 #define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
177 #define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
178 #else
179 #define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
180 #define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
181 #define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
182 #define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
183 #endif
184
185 #define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ
186
187 /*
188 * These are useconds NOT ticks.
189 *
190 */
191 #define mSEC_1 1000
192 #define mSEC_5 (mSEC_1 * 5)
193 #define mSEC_10 (mSEC_1 * 10)
194 #define mSEC_25 (mSEC_1 * 25)
195 #define SEC_1 (mSEC_1 * 1000)
196
197 /*
198 * How long is the timer interval?
199 */
200 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
201 #if TIMER_INTERVAL >= 0x100000
202 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
203 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
204 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
205 #elif TIMER_INTERVAL >= 0x10000
206 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
207 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
208 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
209 #else
210 #define TIMER_RELOAD (TIMER_INTERVAL)
211 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
212 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
213 #endif
214
timer_set_mode(enum clock_event_mode mode,struct clock_event_device * clk)215 static void timer_set_mode(enum clock_event_mode mode,
216 struct clock_event_device *clk)
217 {
218 unsigned long ctrl;
219
220 switch (mode) {
221 case CLOCK_EVT_MODE_PERIODIC:
222 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
223
224 ctrl = TIMER_CTRL_PERIODIC;
225 ctrl |=
226 TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
227 TIMER_CTRL_ENABLE;
228 break;
229 case CLOCK_EVT_MODE_ONESHOT:
230 /* period set, and timer enabled in 'next_event' hook */
231 ctrl = TIMER_CTRL_ONESHOT;
232 ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
233 break;
234 case CLOCK_EVT_MODE_UNUSED:
235 case CLOCK_EVT_MODE_SHUTDOWN:
236 default:
237 ctrl = 0;
238 }
239
240 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
241 }
242
timer_set_next_event(unsigned long evt,struct clock_event_device * unused)243 static int timer_set_next_event(unsigned long evt,
244 struct clock_event_device *unused)
245 {
246 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
247
248 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
249 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
250
251 return 0;
252 }
253
254 static struct clock_event_device timer0_clockevent = {
255 .name = "timer0",
256 .shift = 32,
257 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
258 .set_mode = timer_set_mode,
259 .set_next_event = timer_set_next_event,
260 };
261
262 /*
263 * IRQ handler for the timer
264 */
bcmring_timer_interrupt(int irq,void * dev_id)265 static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
266 {
267 struct clock_event_device *evt = &timer0_clockevent;
268
269 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
270
271 evt->event_handler(evt);
272
273 return IRQ_HANDLED;
274 }
275
276 static struct irqaction bcmring_timer_irq = {
277 .name = "bcmring Timer Tick",
278 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
279 .handler = bcmring_timer_interrupt,
280 };
281
bcmring_get_cycles_timer1(struct clocksource * cs)282 static cycle_t bcmring_get_cycles_timer1(struct clocksource *cs)
283 {
284 return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
285 }
286
bcmring_get_cycles_timer3(struct clocksource * cs)287 static cycle_t bcmring_get_cycles_timer3(struct clocksource *cs)
288 {
289 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
290 }
291
292 static struct clocksource clocksource_bcmring_timer1 = {
293 .name = "timer1",
294 .rating = 200,
295 .read = bcmring_get_cycles_timer1,
296 .mask = CLOCKSOURCE_MASK(32),
297 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
298 };
299
300 static struct clocksource clocksource_bcmring_timer3 = {
301 .name = "timer3",
302 .rating = 100,
303 .read = bcmring_get_cycles_timer3,
304 .mask = CLOCKSOURCE_MASK(32),
305 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
306 };
307
bcmring_clocksource_init(void)308 static int __init bcmring_clocksource_init(void)
309 {
310 /* setup timer1 as free-running clocksource */
311 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
312 writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
313 writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
314 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
315 TIMER1_VA_BASE + TIMER_CTRL);
316
317 clocksource_register_khz(&clocksource_bcmring_timer1,
318 TIMER1_FREQUENCY_MHZ * 1000);
319
320 /* setup timer3 as free-running clocksource */
321 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
322 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
323 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
324 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
325 TIMER3_VA_BASE + TIMER_CTRL);
326
327 clocksource_register_khz(&clocksource_bcmring_timer3,
328 TIMER3_FREQUENCY_KHZ);
329
330 return 0;
331 }
332
333 /*
334 * Set up timer interrupt, and return the current time in seconds.
335 */
bcmring_init_timer(void)336 void __init bcmring_init_timer(void)
337 {
338 printk(KERN_INFO "bcmring_init_timer\n");
339 /*
340 * Initialise to a known state (all timers off)
341 */
342 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
343 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
344 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
345 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
346
347 /*
348 * Make irqs happen for the system timer
349 */
350 setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
351
352 bcmring_clocksource_init();
353
354 timer0_clockevent.mult =
355 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
356 timer0_clockevent.max_delta_ns =
357 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
358 timer0_clockevent.min_delta_ns =
359 clockevent_delta2ns(0xf, &timer0_clockevent);
360
361 timer0_clockevent.cpumask = cpumask_of(0);
362 clockevents_register_device(&timer0_clockevent);
363 }
364
365 struct sys_timer bcmring_timer = {
366 .init = bcmring_init_timer,
367 };
368