1 //------------------------------------------------------------------------------ 2 // Copyright (c) 2010 Atheros Corporation. All rights reserved. 3 // 4 // 5 // Permission to use, copy, modify, and/or distribute this software for any 6 // purpose with or without fee is hereby granted, provided that the above 7 // copyright notice and this permission notice appear in all copies. 8 // 9 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 // 17 // 18 // 19 // Author(s): ="Atheros" 20 //------------------------------------------------------------------------------ 21 22 #ifndef __TARGADDRS_H__ 23 #define __TARGADDRS_H__ 24 25 #ifndef ATH_TARGET 26 #include "athstartpack.h" 27 #endif 28 29 #if defined(AR6002) 30 #include "AR6002/addrs.h" 31 #endif 32 33 /* 34 * AR6K option bits, to enable/disable various features. 35 * By default, all option bits are 0. 36 * These bits can be set in LOCAL_SCRATCH register 0. 37 */ 38 #define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ 39 #define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ 40 #define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ 41 #define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ 42 #define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ 43 #define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ 44 #define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ 45 #define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ 46 47 /* 48 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the 49 * host_interest structure. It must match the address of the _host_interest 50 * symbol (see linker script). 51 * 52 * Host Interest is shared between Host and Target in order to coordinate 53 * between the two, and is intended to remain constant (with additions only 54 * at the end) across software releases. 55 * 56 * All addresses are available here so that it's possible to 57 * write a single binary that works with all Target Types. 58 * May be used in assembler code as well as C. 59 */ 60 #define AR6002_HOST_INTEREST_ADDRESS 0x00500400 61 #define AR6003_HOST_INTEREST_ADDRESS 0x00540600 62 63 64 #define HOST_INTEREST_MAX_SIZE 0x100 65 66 #if !defined(__ASSEMBLER__) 67 struct register_dump_s; 68 struct dbglog_hdr_s; 69 70 /* 71 * These are items that the Host may need to access 72 * via BMI or via the Diagnostic Window. The position 73 * of items in this structure must remain constant 74 * across firmware revisions! 75 * 76 * Types for each item must be fixed size across 77 * target and host platforms. 78 * 79 * More items may be added at the end. 80 */ 81 PREPACK struct host_interest_s { 82 /* 83 * Pointer to application-defined area, if any. 84 * Set by Target application during startup. 85 */ 86 u32 hi_app_host_interest; /* 0x00 */ 87 88 /* Pointer to register dump area, valid after Target crash. */ 89 u32 hi_failure_state; /* 0x04 */ 90 91 /* Pointer to debug logging header */ 92 u32 hi_dbglog_hdr; /* 0x08 */ 93 94 /* Indicates whether or not flash is present on Target. 95 * NB: flash_is_present indicator is here not just 96 * because it might be of interest to the Host; but 97 * also because it's set early on by Target's startup 98 * asm code and we need it to have a special RAM address 99 * so that it doesn't get reinitialized with the rest 100 * of data. 101 */ 102 u32 hi_flash_is_present; /* 0x0c */ 103 104 /* 105 * General-purpose flag bits, similar to AR6000_OPTION_* flags. 106 * Can be used by application rather than by OS. 107 */ 108 u32 hi_option_flag; /* 0x10 */ 109 110 /* 111 * Boolean that determines whether or not to 112 * display messages on the serial port. 113 */ 114 u32 hi_serial_enable; /* 0x14 */ 115 116 /* Start address of Flash DataSet index, if any */ 117 u32 hi_dset_list_head; /* 0x18 */ 118 119 /* Override Target application start address */ 120 u32 hi_app_start; /* 0x1c */ 121 122 /* Clock and voltage tuning */ 123 u32 hi_skip_clock_init; /* 0x20 */ 124 u32 hi_core_clock_setting; /* 0x24 */ 125 u32 hi_cpu_clock_setting; /* 0x28 */ 126 u32 hi_system_sleep_setting; /* 0x2c */ 127 u32 hi_xtal_control_setting; /* 0x30 */ 128 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ 129 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ 130 u32 hi_ref_voltage_trim_setting; /* 0x3c */ 131 u32 hi_clock_info; /* 0x40 */ 132 133 /* 134 * Flash configuration overrides, used only 135 * when firmware is not executing from flash. 136 * (When using flash, modify the global variables 137 * with equivalent names.) 138 */ 139 u32 hi_bank0_addr_value; /* 0x44 */ 140 u32 hi_bank0_read_value; /* 0x48 */ 141 u32 hi_bank0_write_value; /* 0x4c */ 142 u32 hi_bank0_config_value; /* 0x50 */ 143 144 /* Pointer to Board Data */ 145 u32 hi_board_data; /* 0x54 */ 146 u32 hi_board_data_initialized; /* 0x58 */ 147 148 u32 hi_dset_RAM_index_table; /* 0x5c */ 149 150 u32 hi_desired_baud_rate; /* 0x60 */ 151 u32 hi_dbglog_config; /* 0x64 */ 152 u32 hi_end_RAM_reserve_sz; /* 0x68 */ 153 u32 hi_mbox_io_block_sz; /* 0x6c */ 154 155 u32 hi_num_bpatch_streams; /* 0x70 -- unused */ 156 u32 hi_mbox_isr_yield_limit; /* 0x74 */ 157 158 u32 hi_refclk_hz; /* 0x78 */ 159 u32 hi_ext_clk_detected; /* 0x7c */ 160 u32 hi_dbg_uart_txpin; /* 0x80 */ 161 u32 hi_dbg_uart_rxpin; /* 0x84 */ 162 u32 hi_hci_uart_baud; /* 0x88 */ 163 u32 hi_hci_uart_pin_assignments; /* 0x8C */ 164 /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */ 165 u32 hi_hci_uart_baud_scale_val; /* 0x90 */ 166 u32 hi_hci_uart_baud_step_val; /* 0x94 */ 167 168 u32 hi_allocram_start; /* 0x98 */ 169 u32 hi_allocram_sz; /* 0x9c */ 170 u32 hi_hci_bridge_flags; /* 0xa0 */ 171 u32 hi_hci_uart_support_pins; /* 0xa4 */ 172 /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */ 173 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ 174 /* 0xa8 - [0]: 1 = enable, 0 = disable 175 * [1]: 0 = UART FC active low, 1 = UART FC active high 176 * 0xa9 - [7:0]: wakeup timeout in ms 177 * 0xaa, 0xab - [15:0]: idle timeout in ms 178 */ 179 /* Pointer to extended board Data */ 180 u32 hi_board_ext_data; /* 0xac */ 181 u32 hi_board_ext_data_initialized; /* 0xb0 */ 182 } POSTPACK; 183 184 /* Bits defined in hi_option_flag */ 185 #define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ 186 #define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ 187 #define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */ 188 #define HI_OPTION_FW_MODE_LSB 0x08 /* low bit of MODE (see below) */ 189 #define HI_OPTION_FW_MODE_MSB 0x10 /* high bit of MODE (see below) */ 190 #define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */ 191 #define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */ 192 #define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */ 193 #define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */ 194 195 /* 2 bits of hi_option_flag are used to represent 3 modes */ 196 #define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ 197 #define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ 198 #define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ 199 200 /* Fw Mode Mask */ 201 #define HI_OPTION_FW_MODE_MASK 0x3 202 #define HI_OPTION_FW_MODE_SHIFT 0x3 203 204 /* 205 * Intended for use by Host software, this macro returns the Target RAM 206 * address of any item in the host_interest structure. 207 * Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); 208 */ 209 #define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ 210 (u32)((unsigned long)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) 211 212 #define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ 213 (u32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) 214 215 #define HOST_INTEREST_DBGLOG_IS_ENABLED() \ 216 (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG)) 217 218 #define HOST_INTEREST_PROFILE_IS_ENABLED() \ 219 (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE) 220 221 /* Convert a Target virtual address into a Target physical address */ 222 #define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) 223 #define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) 224 #define TARG_VTOP(TargetType, vaddr) \ 225 (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr)) 226 227 /* override REV2 ROM's app start address */ 228 #define AR6002_REV2_APP_START_OVERRIDE 0x911A00 229 #define AR6003_REV1_APP_START_OVERRIDE 0x944c00 230 #define AR6003_REV1_OTP_DATA_ADDRESS 0x542800 231 #define AR6003_REV2_APP_START_OVERRIDE 0x945000 232 #define AR6003_REV2_OTP_DATA_ADDRESS 0x543800 233 #define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600 234 235 236 /* # of u32 entries in targregs, used by DIAG_FETCH_TARG_REGS */ 237 #define AR6003_FETCH_TARG_REGS_COUNT 64 238 239 #endif /* !__ASSEMBLER__ */ 240 241 #ifndef ATH_TARGET 242 #include "athendpack.h" 243 #endif 244 245 #endif /* __TARGADDRS_H__ */ 246