Home
last modified time | relevance | path

Searched refs:gtt_offset (Results 1 – 16 of 16) sorted by relevance

/linux-2.6.39/drivers/gpu/drm/i915/
Di915_gem_tiling.c248 if (obj->gtt_offset & ~I915_FENCE_START_MASK) in i915_gem_object_fence_ok()
251 if (obj->gtt_offset & ~I830_FENCE_START_MASK) in i915_gem_object_fence_ok()
270 if (obj->gtt_offset & (size - 1)) in i915_gem_object_fence_ok()
345 (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end && in i915_gem_set_tiling()
352 if (obj->gtt_offset & (unfenced_alignment - 1)) in i915_gem_set_tiling()
Di915_gem_debug.c148 __func__, obj, obj->gtt_offset, handle, in i915_gem_object_check_coherency()
151 gtt_mapping = ioremap(dev->agp->base + obj->gtt_offset, obj->base.size); in i915_gem_object_check_coherency()
175 (int)(obj->gtt_offset + in i915_gem_object_check_coherency()
Dintel_ringbuffer.c154 I915_WRITE_START(ring, obj->gtt_offset); in init_ring_common()
186 I915_READ_START(ring) != obj->gtt_offset || in init_ring_common()
216 u32 gtt_offset; member
245 pc->gtt_offset = obj->gtt_offset; in init_pipe_control()
402 u32 scratch_addr = pc->gtt_offset + 128; in pc_render_add_request()
419 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); in pc_render_add_request()
436 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); in pc_render_add_request()
769 ring->status_page.gfx_addr = obj->gtt_offset; in init_status_page()
826 ring->map.offset = dev->agp->base + obj->gtt_offset; in intel_init_ring_buffer()
1212 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); in blt_ring_begin()
Dintel_fb.c139 info->fix.smem_start = dev->mode_config.fb_base + obj->gtt_offset; in intelfb_create()
142 info->screen_base = ioremap_wc(dev->agp->base + obj->gtt_offset, size); in intelfb_create()
162 obj->gtt_offset, obj); in intelfb_create()
Di915_gem.c597 loff_t gtt_base, int gtt_offset, in slow_kernel_write() argument
607 memcpy_toio(dst_vaddr + gtt_offset, in slow_kernel_write()
634 offset = obj->gtt_offset + args->offset; in i915_gem_gtt_pwrite_fast()
723 offset = obj->gtt_offset + args->offset; in i915_gem_gtt_pwrite_slow()
1241 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + in i915_gem_fault()
2208 obj->gtt_offset = 0; in i915_gem_object_unbind()
2286 val = (uint64_t)((obj->gtt_offset + size - 4096) & in sandybridge_write_fence_reg()
2288 val |= obj->gtt_offset & 0xfffff000; in sandybridge_write_fence_reg()
2323 val = (uint64_t)((obj->gtt_offset + size - 4096) & in i965_write_fence_reg()
2325 val |= obj->gtt_offset & 0xfffff000; in i965_write_fence_reg()
[all …]
Di915_debugfs.c139 obj->gtt_offset, (unsigned int)obj->gtt_space->size); in describe_obj()
355 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); in i915_gem_pageflip_info()
360 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); in i915_gem_pageflip_info()
572 obj->gtt_offset + page * PAGE_SIZE); in i915_dump_object()
593 seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset); in i915_batchbuffer_info()
707 err->gtt_offset, in print_error_buffers()
797 obj->gtt_offset); in i915_error_state()
813 obj->gtt_offset); in i915_error_state()
Dintel_overlay.c202 overlay->reg_bo->gtt_offset); in intel_overlay_map_regs()
824 regs->OBUF_0Y = new_bo->gtt_offset + params-> offset_Y; in intel_overlay_do_put_image()
838 regs->OBUF_0U = new_bo->gtt_offset + params->offset_U; in intel_overlay_do_put_image()
839 regs->OBUF_0V = new_bo->gtt_offset + params->offset_V; in intel_overlay_do_put_image()
1434 overlay->flip_addr = reg_bo->gtt_offset; in intel_setup_overlay()
1508 overlay->reg_bo->gtt_offset); in intel_overlay_map_regs_atomic()
1541 error->base = (long) overlay->reg_bo->gtt_offset; in intel_overlay_capture_error_state()
Di915_irq.c591 reloc_offset = src->gtt_offset; in i915_error_object_create()
613 dst->gtt_offset = src->gtt_offset; in i915_error_object_create()
666 err->gtt_offset = obj->gtt_offset; in capture_bo_list()
1074 stall_detected = I915_READ(dspsurf) == obj->gtt_offset; in i915_pageflip_stall_check()
1077 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + in i915_pageflip_stall_check()
Di915_gem_execbuffer.c287 target_offset = to_intel_bo(target_obj)->gtt_offset; in i915_gem_execbuffer_relocate_entry()
379 reloc->offset += obj->gtt_offset; in i915_gem_execbuffer_relocate_entry()
534 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || in i915_gem_execbuffer_reserve()
583 entry->offset = obj->gtt_offset; in i915_gem_execbuffer_reserve()
1167 exec_start = batch_obj->gtt_offset + args->batch_start_offset; in i915_gem_do_execbuffer()
Di915_drv.h175 u32 gtt_offset; member
182 u32 gtt_offset; member
814 uint32_t gtt_offset; member
Dintel_display.c1862 dev_priv->cfb_offset == obj->gtt_offset && in ironlake_enable_fbc()
1873 dev_priv->cfb_offset = obj->gtt_offset; in ironlake_enable_fbc()
1889 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); in ironlake_enable_fbc()
2189 Start = obj->gtt_offset; in intel_pipe_set_base_atomic()
5373 addr = obj->gtt_offset; in intel_crtc_cursor_set()
6155 OUT_RING(obj->gtt_offset + offset); in intel_crtc_page_flip()
6163 OUT_RING(obj->gtt_offset + offset); in intel_crtc_page_flip()
6176 OUT_RING(obj->gtt_offset | obj->tiling_mode); in intel_crtc_page_flip()
6191 OUT_RING(obj->gtt_offset); in intel_crtc_page_flip()
7206 OUT_RING(dev_priv->renderctx->gtt_offset | in ironlake_enable_rc6()
[all …]
/linux-2.6.39/drivers/gpu/drm/
Ddrm_agpsupport.c437 uint32_t gtt_offset, in drm_agp_bind_pages() argument
458 ret = agp_bind_memory(mem, gtt_offset / PAGE_SIZE); in drm_agp_bind_pages()
/linux-2.6.39/drivers/char/agp/
Dintel-gtt.c1199 u32 gtt_offset; in i9xx_setup() local
1204 gtt_offset = MB(2); in i9xx_setup()
1208 gtt_offset = KB(512); in i9xx_setup()
1211 intel_private.gtt_bus_addr = reg_addr + gtt_offset; in i9xx_setup()
/linux-2.6.39/drivers/staging/gma500/
Dpsb_drm.h341 unsigned long gtt_offset; member
Dpsb_ttm_glue.c340 arg->gtt_offset = bo->offset; in psb_getpageaddrs_ioctl()
/linux-2.6.39/include/drm/
DdrmP.h1262 uint32_t gtt_offset,