Searched refs:divider_u71 (Results 1 – 1 of 1) sorted by relevance
200 s64 divider_u71 = parent_rate * 2; in clk_div71_get_divider() local201 divider_u71 += rate - 1; in clk_div71_get_divider()202 do_div(divider_u71, rate); in clk_div71_get_divider()204 if (divider_u71 - 2 < 0) in clk_div71_get_divider()207 if (divider_u71 - 2 > 255) in clk_div71_get_divider()210 return divider_u71 - 2; in clk_div71_get_divider()859 int divider_u71; in tegra2_pll_div_clk_set_rate() local865 divider_u71 = clk_div71_get_divider(parent_rate, rate); in tegra2_pll_div_clk_set_rate()866 if (divider_u71 >= 0) { in tegra2_pll_div_clk_set_rate()874 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; in tegra2_pll_div_clk_set_rate()[all …]