| /linux-2.6.39/drivers/edac/ |
| D | edac_mc.c | 73 mci->nr_csrows, mci->csrows); in edac_mc_dump_mci()
190 mci->csrows = csi; in edac_mc_alloc()
520 edac_mc_dump_csrow(&mci->csrows[i]); in edac_mc_add_mc()
521 for (j = 0; j < mci->csrows[i].nr_channels; j++) in edac_mc_add_mc()
522 edac_mc_dump_channel(&mci->csrows[i]. in edac_mc_add_mc()
643 struct csrow_info *csrows = mci->csrows; in edac_mc_find_csrow_by_page() local
650 struct csrow_info *csrow = &csrows[i]; in edac_mc_find_csrow_by_page()
699 if (channel >= mci->csrows[row].nr_channels || channel < 0) { in edac_mc_handle_ce()
704 mci->csrows[row].nr_channels); in edac_mc_handle_ce()
715 mci->csrows[row].grain, syndrome, row, channel, in edac_mc_handle_ce()
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| D | i5100_edac.c | 436 csrow, mci->csrows[csrow].channels[0].label, msg); in i5100_handle_ce()
439 mci->csrows[csrow].ce_count++; in i5100_handle_ce()
440 mci->csrows[csrow].channels[0].ce_count++; in i5100_handle_ce()
458 csrow, mci->csrows[csrow].channels[0].label, msg); in i5100_handle_ue()
461 mci->csrows[csrow].ue_count++; in i5100_handle_ue()
856 mci->csrows[i].first_page = total_pages; in i5100_init_csrows()
857 mci->csrows[i].last_page = total_pages + npages - 1; in i5100_init_csrows()
858 mci->csrows[i].page_mask = 0UL; in i5100_init_csrows()
860 mci->csrows[i].nr_pages = npages; in i5100_init_csrows()
861 mci->csrows[i].grain = 32; in i5100_init_csrows()
[all …]
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| D | amd76x_edac.c | 149 edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0, in amd76x_process_error_info()
162 edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0, in amd76x_process_error_info()
193 csrow = &mci->csrows[index]; in amd76x_init_csrows()
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| D | pasemi_edac.c | 113 edac_mc_handle_ue(mci, mci->csrows[cs].first_page, 0, in pasemi_edac_process_error_info()
119 edac_mc_handle_ce(mci, mci->csrows[cs].first_page, 0, in pasemi_edac_process_error_info()
142 csrow = &mci->csrows[index]; in pasemi_edac_init_csrows()
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| D | cell_edac.c | 36 struct csrow_info *csrow = &mci->csrows[0]; in cell_edac_count_ce()
58 struct csrow_info *csrow = &mci->csrows[0]; in cell_edac_count_ue()
126 struct csrow_info *csrow = &mci->csrows[0]; in cell_edac_init_csrows()
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| D | edac_mc_sysfs.c | 426 struct csrow_info *ri = &mci->csrows[row]; in mci_reset_counters_store()
526 struct csrow_info *csrow = &mci->csrows[csrow_idx]; in mci_size_mb_show()
937 csrow = &mci->csrows[i]; in edac_create_sysfs_mci_device()
956 kobject_put(&mci->csrows[i].kobj); in edac_create_sysfs_mci_device()
983 if (mci->csrows[i].nr_pages > 0) { in edac_remove_sysfs_mci_device()
985 kobject_put(&mci->csrows[i].kobj); in edac_remove_sysfs_mci_device()
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| D | i3000_edac.c | 239 multi_chan = mci->csrows[0].nr_channels - 1; in i3000_process_error_info()
381 struct csrow_info *csrow = &mci->csrows[i]; in i3000_probe1()
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| D | i82875p_edac.c | 229 multi_chan = mci->csrows[0].nr_channels - 1; in i82875p_process_error_info()
361 csrow = &mci->csrows[index]; in i82875p_init_csrows()
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| D | i7core_edac.c | 503 unsigned *csrows) in i7core_get_active_channels() argument
510 *csrows = 0; in i7core_get_active_channels()
553 (*csrows)++; in i7core_get_active_channels()
685 csr = &mci->csrows[csrow]; in get_dimm_config()
1928 int rc, channels, csrows; in i7core_register_mci() local
1931 rc = i7core_get_active_channels(i7core_dev->socket, &channels, &csrows); in i7core_register_mci()
1936 mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, i7core_dev->socket); in i7core_register_mci()
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| D | i82975x_edac.c | 283 multi_chan = mci->csrows[0].nr_channels - 1; in i82975x_process_error_info()
380 csrow = &mci->csrows[index]; in i82975x_init_csrows()
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| D | tile_edac.c | 84 struct csrow_info *csrow = &mci->csrows[0]; in tile_edac_init_csrows()
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| D | cpc925_edac.c | 348 csrow = &mci->csrows[index]; in cpc925_init_csrows()
459 if (mci->csrows[rank].first_page == 0) { in cpc925_mc_get_pfn()
467 pa = mci->csrows[rank].first_page << PAGE_SHIFT; in cpc925_mc_get_pfn()
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| D | i82860_edac.c | 155 csrow = &mci->csrows[index]; in i82860_init_csrows()
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| D | r82600_edac.c | 229 csrow = &mci->csrows[index]; in r82600_init_csrows()
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| D | i82443bxgx_edac.c | 199 csrow = &mci->csrows[index]; in i82443bxgx_init_csrows()
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| D | i3200_edac.c | 370 struct csrow_info *csrow = &mci->csrows[i]; in i3200_probe1()
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| D | x38_edac.c | 369 struct csrow_info *csrow = &mci->csrows[i]; in x38_probe1()
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| D | e7xxx_edac.c | 370 csrow = &mci->csrows[index]; in e7xxx_init_csrows()
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| D | edac_core.h | 405 struct csrow_info *csrows; member
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| D | mpc85xx_edac.c | 816 csrow = &mci->csrows[row_index]; in mpc85xx_mc_check()
931 csrow = &mci->csrows[index]; in mpc85xx_init_csrows()
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| D | ppc4xx_edac.c | 922 struct csrow_info *csi = &mci->csrows[row]; in ppc4xx_edac_init_csrows()
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| D | i7300_edac.c | 815 p_csrow = &mci->csrows[slot]; in i7300_init_csrows()
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| D | mv64x60_edac.c | 666 csrow = &mci->csrows[0]; in mv64x60_init_csrows()
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| D | i5400_edac.c | 1149 p_csrow = &mci->csrows[csrow]; in i5400_init_csrows()
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| /linux-2.6.39/Documentation/ |
| D | edac.txt | 152 be multiple csrows and multiple channels.
154 Memory controllers allow for several csrows, with 8 csrows being a typical value.
155 Yet, the actual number of csrows depends on the electrical "loading"
184 are channel 1. Notice that there are two csrows possible on a
185 physical DIMM. These csrows are allocated their csrow assignment
187 is placed in each Channel, the csrows cross both DIMMs.
740 The minimum known unity is DIMMs. There are no information about csrows.
741 As EDAC API maps the minimum unity is csrows, the driver sequencially
742 maps channel/dimm into different csrows.
852 What happens here is that errors on different csrows, but at the same
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