Searched refs:chipcHw_REG_DIV_CLOCK_DIV_256 (Results 1 – 2 of 2) sorted by relevance
188 #define chipcHw_REG_DIV_CLOCK_DIV_256 0x00000000 /* NON-PLL clock post-divide by … macro
486 …rl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divi… in chipcHw_setClockFrequency()